Abstract: A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads.

Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and 10 a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.

Abstract: A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip.

Abstract: A stack package includes a printed circuit board; at least two semiconductor chips stacked on the printed circuit board, each having first re-distribution lines formed on the upper surface thereof and connected to bonding pads, through silicon vias which are formed therethrough and connected to the first re-distribution lines, and second re-distribution lines formed on the lower surface thereof and connected to the through silicon vias; first and second solder balls interposed between the first and second re-distribution lines which face each other and between the first re-distribution lines of the lowermost semiconductor chip and electrode terminals of the printed circuit board; a molding material for molding the upper surface of the printed circuit board including the stacked semiconductor chips; and third solder balls attached to ball lands formed on the lower surface of the printed circuit board.

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract: A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

Abstract: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Abstract: A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals.

Abstract: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

Abstract: To manufacture a wafer level stack package, first and second wafers having first and second via patterns are prepared. The second wafer is attached to the first wafer such that the front sides of the first and second wafers face each other and the first and second via patterns are connected to each other. The back side of the second wafer is ground and etched such that the lower ends of the second via patterns are exposed and projected. The back side of the first wafer is ground and etched such that the lower ends of the first via patterns are exposed and projected. A chip level stack structure is formed by sawing a wafer level stack structure having the stacked wafers into a chip level. The chip level stack structure is attached to a substrate having electrode terminals.

Abstract: A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.

Abstract: A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region.

Abstract: A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern.

Abstract: A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Abstract: A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip.

Abstract: A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.

Abstract: A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.

Abstract: A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

Abstract: A stack package includes an edge-pad-type first semiconductor chip having bonding pads arranged near the edges thereof. A pattern die is placed on the first semiconductor chip. The pattern die is smaller in size than the first semiconductor chip and has line-type-redistribution parts formed thereon. An edge-pad-type second semiconductor chip smaller in size than the pattern die is placed on the pattern die. Bonding wires electrically connect the bonding pads of the first semiconductor chip and the redistribution parts of the pattern die and also electrically connect the redistribution parts of the pattern die and bonding pads of the second semiconductor chip.