Abstract: The present disclosure relates to a display panel and a display device using the same. Between first and second pixel areas having different pixels per inch, a third pixel area is provided to have the same pixels per inch as the first pixel area. In the third pixel area, some of pixels emit light as ON pixels, and remaining background pixels except for the ON pixels are driven as OFF pixels or low luminance pixels.

Abstract: Disclosed are a display panel and a display device including the same according to an embodiment. A display panel according to the embodiment includes: a display area in which a plurality of first pixels are arranged at a first pixels per inch (PPI); and a sensing area in which a plurality of second pixels are arranged at a second PPI that is lower than the first PPI, wherein the first pixels of the display area and the second pixels of the sensing area are arranged adjacent to each other at a boundary between the display area and the sensing area, the second pixel includes red, green, and blue sub-pixels, and at least one of the red and green sub-pixels of the second pixel is arranged closest to the first pixel.

Abstract: Disclosed is a method of purifying boron nitride nanotubes through a simplified process. Specifically, the method includes preparing a starting solution containing boron nitride nanotubes (BNNTs), a dispersant and a solvent, centrifuging the starting solution or allowing the starting solution to stand to collect a supernatant, adding an acid to the supernatant and filtering a resulting product.

Abstract: An earthwork target model generation system comprises a processor. The processor of the earthwork target model generation system stores a three-dimensional topography shape model and drill boring data in the target model generation system, generates a three-dimensional ground model using the three-dimensional topography shape model and the drill boring data, generates three-dimensional normal surface information in consideration of a design condition for each rock quality using the three-dimensional ground model, and sets the design condition.

Abstract: Disclosed is a method of purifying boron nitride nanotubes through a simplified process. Specifically, the method includes preparing a starting solution containing boron nitride nanotubes (BNNTs), a dispersant and a solvent, centrifuging the starting solution or allowing the starting solution to stand to collect a supernatant, adding an acid to the supernatant and filtering a resulting product.

Abstract: The present disclosure relates to a three-dimensional ground model generation and an automated earthwork target model generation system based on a parameter input.

Abstract: This specification discloses a quantum public-key cryptosystem. The quantum public-key cryptosystem may use two rotation operators R{circumflex over (n)}(?) and R{circumflex over (m)}(?) satisfying a cyclic evolution. The two rotation operators R{circumflex over (n)}(?) and R{circumflex over (m)}(?) do not have a commutation relation or an anti-commutation relation with each other. The commutation relation or the anti-commutation relation is established when either of the following conditions is satisfied: ?=2i?, ?=2j?, or {circumflex over (n)}·{circumflex over (m)}=1 (i, j=integer), and ?=(2k+1)?, ?=(2l+1)?, or {circumflex over (n)}·{circumflex over (m)}=0 (k, l=integer).

Abstract: An unmanned control system of an operation lever for operating a device includes: a mountable operation unit which is attachably and separably coupled to an operation lever for operating a device and manipulates the operation lever; and an operation unit control part which moves the operation lever coupled to the mountable operation unit by remotely controlling the mountable operation unit, in which the mountable operation unit has the same degree of freedom as the operation lever. The unmanned control system may lower a center of gravity of the mountable operation unit, thereby precisely controlling the operation lever and improving intuition with respect to the movement of the operation lever and the mountable unit.

Abstract: A low gloss ASA-based resin composition having excellent weatherability and heat resistance is provided. The low gloss ASA-based resin composition is obtained by blending a general SAN copolymer, a heat-resistant SAN copolymer, a crosslinked aromatic vinyl compound-cyanide vinyl compound copolymer, and an amorphous inorganic material with large diameter and extra-large diameter ASA graft copolymers at a predetermined composition ratio. The low gloss ASA-based resin composition is useful in the manufacture of a high-quality molded article in which gloss characteristics are uniformly exhibited because impact resistance, heat resistance, flowability, weatherability, and low gloss characteristics are all excellent, and particularly, the gloss deviation on the entire surface of the injection molded article is significantly reduced.

Abstract: A low gloss ASA-based resin composition having excellent weatherability and heat resistance is provided. The low gloss ASA-based resin composition is obtained by blending a general SAN copolymer, a heat-resistant SAN copolymer, a crosslinked aromatic vinyl compound-cyanide vinyl compound copolymer, and an amorphous inorganic material with large diameter and extra-large diameter ASA graft copolymers at a predetermined composition ratio. The low gloss ASA-based resin composition is useful in the manufacture of a high-quality molded article in which gloss characteristics are uniformly exhibited because impact resistance, heat resistance, flowability, weatherability, and low gloss characteristics are all excellent, and particularly, the gloss deviation on the entire surface of the injection molded article is significantly reduced.

Abstract: A semiconductor device may include a pattern detector configured to select any one of a plurality of stride patterns as a detect pattern by referring to an input address, and the pattern detector may be configured to generate a prefetch address. The semiconductor device may also include a prefetch controller configured to generate a prefetch request according to the prefetch address generated by the pattern detector. The semiconductor device may also include a first storage unit configured to store prefetch data provided from a memory device according to the prefetch request generated by the prefetch controller, and a second storage unit configured to store prefetch data removed from the first storage unit.

Abstract: An unmanned control system of an operation lever for operating a device includes: a mountable operation unit which is attachably and separably coupled to an operation lever for operating a device and manipulates the operation lever; and an operation unit control part which moves the operation lever coupled to the mountable operation unit by remotely controlling the mountable operation unit, in which the mountable operation unit has the same degree of freedom as the operation lever. The unmanned control system may lower a center of gravity of the mountable operation unit, thereby precisely controlling the operation lever and improving intuition with respect to the movement of the operation lever and the mountable unit.

Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.

Abstract: A semiconductor device may include a pattern detector configured to select any one of a plurality of stride patterns as a detect pattern by referring to an input address, and the pattern detector may be configured to generate a prefetch address. The semiconductor device may also include a prefetch controller configured to generate a prefetch request according to the prefetch address generated by the pattern detector. The semiconductor device may also include a first storage unit configured to store prefetch data provided from a memory device according to the prefetch request generated by the prefetch controller, and a second storage unit configured to store prefetch data removed from the first storage unit.

Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.

Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.

Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.

Abstract: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.

Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.

Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.