Patents by Inventor Min-Sung Kang
Min-Sung Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8987907Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.Type: GrantFiled: February 26, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Min-sung Kang, Se-myeong Jang
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Publication number: 20140379995Abstract: A semiconductor device may include a pattern detector configured to select any one of a plurality of stride patterns as a detect pattern by referring to an input address, and the pattern detector may be configured to generate a prefetch address. The semiconductor device may also include a prefetch controller configured to generate a prefetch request according to the prefetch address generated by the pattern detector. The semiconductor device may also include a first storage unit configured to store prefetch data provided from a memory device according to the prefetch request generated by the prefetch controller, and a second storage unit configured to store prefetch data removed from the first storage unit.Type: ApplicationFiled: June 10, 2014Publication date: December 25, 2014Inventors: Jung-Hyun KWON, Min-Sung KANG
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Patent number: 8809993Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.Type: GrantFiled: February 21, 2013Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sei-lyn Kwak, Se-myeong Jang, Min-sung Kang, Yun-jae Lee, Hyeon-kyu Lee
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Publication number: 20130241027Abstract: A semiconductor device can include an isolation region that defines a plurality of active regions. The plurality of active regions can include an upper surface having a short axis in a first direction and a long axis in a second direction. The plurality of active regions can be repeatedly disposed along the first direction and along the second direction, and can be spaced apart from each other. The isolation region can include a first insulating layer being in contact with side walls of a short axis pair of active regions which can be the closest active regions in the first direction among the plurality of active regions, and continuously extending along a first shortest distance between the short axis pair of active regions.Type: ApplicationFiled: February 21, 2013Publication date: September 19, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Sei-lyn Kwak, Se-myeong Jang, Min-sung Kang, Yun-jae Lee, Hyeon-kyu Lee
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Publication number: 20130241065Abstract: A semiconductor device may include a semiconductor layer including at least one unit device, a first interconnection on the semiconductor layer and electrically connected to the at least one unit device, a diffusion barrier layer on the first interconnection, an intermetallic dielectric layer on the diffusion barrier layer, a plug in a first region of the intermetallic dielectric layer and passing through the diffusion barrier layer so that a bottom surface thereof contacts the first interconnection, and a first dummy plug in a second region of the intermetallic dielectric layer, passing through the diffusion barrier layer, and disposed apart from the first interconnection so that a bottom surface of the first dummy plug does not contact the first interconnection.Type: ApplicationFiled: February 26, 2013Publication date: September 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-sung KANG, Se-myeong JANG
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Patent number: 8299517Abstract: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.Type: GrantFiled: February 20, 2008Date of Patent: October 30, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ho Jang, Yong-Jin Choi, Min-Sung Kang, Kwang-Woo Lee
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Patent number: 8293644Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.Type: GrantFiled: February 22, 2010Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Se-myeong Jang, Min-sung Kang
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Publication number: 20110053369Abstract: Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer.Type: ApplicationFiled: February 22, 2010Publication date: March 3, 2011Inventors: Se-myeong Jang, Min-sung Kang
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Patent number: 7750432Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.Type: GrantFiled: September 12, 2008Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
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Patent number: 7553748Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.Type: GrantFiled: August 10, 2006Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Ho Jang, Sang-Ho Song, Sung-Sam Lee, Min-Sung Kang, Won-Tae Park, Min-Young Shim
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Publication number: 20090014829Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.Type: ApplicationFiled: September 12, 2008Publication date: January 15, 2009Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
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Patent number: 7439102Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.Type: GrantFiled: November 10, 2006Date of Patent: October 21, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
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Publication number: 20080203455Abstract: A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure.Type: ApplicationFiled: February 20, 2008Publication date: August 28, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Ho JANG, Yong-Jin CHOI, Min-Sung KANG, Kwang-Woo LEE
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Publication number: 20070057342Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.Type: ApplicationFiled: November 10, 2006Publication date: March 15, 2007Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
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Publication number: 20070042583Abstract: According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.Type: ApplicationFiled: August 10, 2006Publication date: February 22, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Ho JANG, Sang-Ho SONG, Sung-Sam LEE, Min-Sung KANG, Won-Tae PARK, Min-Young SHIM
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Patent number: 7154160Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.Type: GrantFiled: October 7, 2004Date of Patent: December 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
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Publication number: 20050082635Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.Type: ApplicationFiled: October 7, 2004Publication date: April 21, 2005Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin