Abstract: A method for forming a semiconductor structure is provided. The method includes forming a channel layer over a substrate, forming a source/drain feature adjoining the channel layer, and forming a gate stack over the channel layer. The gate stack includes a gate dielectric layer and a gate electrode layer nested within the gate dielectric layer. The method also includes recessing the gate dielectric layer to expose the gate electrode layer, forming a filling layer over the gate stack and the source/drain feature, and forming a contact plug through the filling layer and on the source/drain feature.

Abstract: A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.

Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Abstract: A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: A method comprises forming a source/drain region on a substrate; forming a dielectric layer over the source/drain region; forming a contact hole in the dielectric layer; forming a contact hole liner in the contact hole; removing a first portion of the contact hole liner to expose a sidewall of the contact hole; etching the exposed sidewall of the contact hole to laterally expand the contact hole; and forming a contact plug in the laterally expanded contact hole.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.