Abstract: The present disclosure provides a method that includes forming an isolation feature in a semiconductor substrate; forming a first fin and a second fin on the semiconductor substrate, wherein the first and second fins are laterally separated by the isolation feature; and forming an elongated contact feature landing on the first and second fins. The elongated contact feature is further embedded in the isolation feature, enclosing an air gap vertically between the contact feature and the isolation feature.

Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.

Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.

Abstract: A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.