Patents by Inventor Min Yao

Min Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965217
    Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 23, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
  • Publication number: 20240124677
    Abstract: The present disclosure relates to the technical field of microbial applications, and in particular to Roseibium aggregatum and use, a culture method and a method for degrading plastics thereof. The Roseibium aggregatum provided by the present disclosure has an accession number of CGMCC No. 25240, and has a function of degrading plastic, which can degrade plastic in seawater with high degradation efficiency.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 18, 2024
    Applicant: HAINAN TROPICAL OCEAN UNIVERSITY
    Inventors: Jun MU, Lingdi YAO, Min LIU
  • Patent number: 11958943
    Abstract: The present disclosure relates to the technical field of microbial applications, and in particular to Roseibium aggregatum and use, a culture method and a method for degrading plastics thereof. The Roseibium aggregatum provided by the present disclosure has an accession number of CGMCC No. 25240, and has a function of degrading plastic, which can degrade plastic in seawater with high degradation efficiency.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: April 16, 2024
    Assignee: HAINAN TROPICAL OCEAN UNIVERSITY
    Inventors: Jun Mu, Lingdi Yao, Min Liu
  • Publication number: 20240115292
    Abstract: Exemplary embodiments of apparatus and method for obtaining one or more portions of biological tissue (“micrografts”) to form grafts are provided. For example, a hollow tube can be inserted into tissue at a donor site, and a pin provided within the tube can facilitate controlled removal of the micrograft from the tube. Micrografts can be harvested and directly implanted into an overlying biocompatible matrix through coordinated motion of the tube and pin. A needle can be provided around the tube to facilitate a direct implantation of a micrograft into a remote recipient site or matrix. The exemplary apparatus can include a plurality of such tubes and pins for simultaneous harvesting and/or implanting of a plurality of micrografts. The harvested micrografts can have a small dimension, e.g., less than about 1 mm, which can promote healing of the donor site and/or viability of the harvested tissue.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 11, 2024
    Inventors: Richard Rox Anderson, William A. Farinelli, Walfre Franco, Joshua Tam, Fernanda H. Sakamoto, Apostolos G. Doukas, Martin Purschke, Min Yao
  • Patent number: 11955392
    Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Wen Chang, Yu-Hsien Li, Min-Tar Liu, Yuan-Yao Chang
  • Publication number: 20240105933
    Abstract: The present disclosure discloses a high-safety ternary positive electrode material and a method for preparing the same; wherein the ternary positive electrode material has a chemical composition of Lia(NixCoyMn1-x-y)1-bMbO2-cAc, wherein 0.75?a?1.2, 0.75?x<1, 0<y?0.15, 1?x?y>0, 0?b?0.01, 0?c?0.2, M is one or more selected from the group consisting of Al, Zr, Ti, Y, Sr, W and Mg, and A is one or more selected from the group consisting of S, F and N; and CMn?(1?x?y)?0.07; CCo?y?0.05; 0?[CMn?(1?x?y)]/(CCo?y)?2.0. The ternary positive electrode material of the present disclosure is a high-nickel single crystal material with gradient concentration; it has the advantages of high capacity and high thermal stability, and the preparation method is simple, and is suitable for large-scale production.
    Type: Application
    Filed: May 18, 2023
    Publication date: March 28, 2024
    Inventors: Hui CAO, Yi YAO, Min HOU, Chan LIU, Yingying GUO, Dandan CHEN
  • Publication number: 20240096721
    Abstract: An electronic package of which the manufacturing method is to dispose an electronic element on a circuit portion, encapsulate the electronic element with an Ajinomoto build-up film (ABF) used as an encapsulating layer, form a wiring layer on the encapsulating layer, and form a conductive via in the encapsulating layer. Therefore, the wiring layer can be well bonded onto the encapsulating layer as the ABF material is used as the encapsulating layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Kuang LAI, Andrew C. CHANG, Min-Yao CHEN
  • Publication number: 20240096776
    Abstract: A package substrate is provided and includes a core board body and a first circuit structure and a second circuit structure disposed on opposite sides of the core board body, where the number of wiring layers of the second circuit structure is different from the number of wiring layers of the first circuit structure, so that the package substrate is asymmetrical. The first circuit structure and the second circuit structure are designed according to the thickness and coefficient of thermal expansion of the first dielectric layer of the first circuit structure and the second dielectric layer of the second circuit structure, so as to prevent the problem of warping from occurring to the package substrate.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 21, 2024
    Inventors: Andrew C. CHANG, Min-Yao CHEN, Sung-Kun LIN
  • Publication number: 20240088054
    Abstract: A carrier structure is provided with a plurality of package substrates connected via connecting sections, and a functional element and a groove are formed on the connecting section, such that the groove is located between the package substrate and the functional element. Therefore, when a cladding layer covering a chip is formed on the package substrate, the groove can accommodate a glue material overflowing from the cladding layer to prevent the glue material from contaminating the functional element.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 14, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shu-Ting LAI, Chiu-Lien LI, Che-Min SU, Chun-Huan HUNG, Mu-Hung HSIEH, Cheng-Han YAO, Fajanilan Darcyjo Directo, Cheng-Liang HSU
  • Patent number: 11929295
    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Richard C. Stamey, Chu Aun Lim, Jimin Yao
  • Patent number: 11919904
    Abstract: The present application provides sulfonyl amide compounds, which are inhibitors of cyclin-dependent kinase 2 (CDK2), as well as pharmaceutical compositions thereof, and methods of treating cancer using the same.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 5, 2024
    Assignee: Incyte Corporation
    Inventors: Alexander Sokolsky, Sarah Winterton, Liangxing Wu, Wenqing Yao, Min Ye, Yingnan Chen, Margaret Favata, Yvonne Lo
  • Publication number: 20240067566
    Abstract: A method for preparing Portland cement includes: respectively weighing iron slag, copper slag, vanadium slag, and nickel slag and grinding, to yield prefabricated iron slag, prefabricated copper slag, prefabricated vanadium slag, and prefabricated nickel slag; weighing mica and kaolinite, mixing, and grinding to obtain aluminous raw materials; evenly mixing the prefabricated iron slag and the aluminous raw materials, and calcining, to yield an iron-aluminum eutectic mineral; weighing the marble, fluorite, dolomite, and quartz, evenly mixing the marble, fluorite, dolomite, and quartz with the prefabricated copper slag, prefabricated vanadium slag, and prefabricated nickel slag to yield a first mixture; grinding the iron-aluminum eutectic mineral to yield powders, and calcining a second mixture of the first mixture and the powders, to yield the cement clinker; and cooling the cement clinker, and grinding a third mixture of the cooled cement clinker and the gypsum, to yield the Portland cement.
    Type: Application
    Filed: May 11, 2023
    Publication date: February 29, 2024
    Inventors: Kunyue ZHANG, Xiao ZHI, Min WANG, Zhaijun WEN, Xiaopeng AN, Wen HUANG, Guang YAO, Yang YU, Xin SHEN
  • Publication number: 20240021438
    Abstract: A manufacturing method of a package substrate is provided, the manufacturing method includes forming a first circuit layer on a first metal layer; forming a dielectric layer on the first metal layer and the first circuit layer; forming a second metal layer on the dielectric layer; forming a plurality of conductive blind vias in the dielectric layer and forming a second circuit layer on the second metal layer, where the plurality of conductive blind vias are electrically connected to the first circuit layer and the second circuit layer; and removing the first metal layer and a portion of the second metal layer simultaneously. Therefore, in the manufacturing method, the first metal layer and the second metal layer can be removed by one etching process, such that the time for manufacturing the package substrate can be greatly reduced to increase production quantity.
    Type: Application
    Filed: May 17, 2023
    Publication date: January 18, 2024
    Inventors: Andrew C. CHANG, Min-Yao CHEN, Sung-Kun LIN
  • Publication number: 20240011045
    Abstract: The present invention provides novel DNA molecules and constructs, including their nucleotide sequences, useful for expressing proteins in plants to promote symbiotic infection. The invention also provides plants and plant cells transgenic plants, plant cells, plant parts, seeds, and commodity products comprising the DNA molecules operably linked to heterologous transcribable polynucleotides, along with methods of their use.
    Type: Application
    Filed: May 18, 2023
    Publication date: January 11, 2024
    Inventors: Giles Edward Dixon Oldroyd, Katharina Schiessl, Tak Lee, Min-yao Jhu
  • Patent number: 11848296
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
  • Publication number: 20230400648
    Abstract: The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Min-Yao CHENG, Hung-Yi LIN
  • Patent number: 11832845
    Abstract: Exemplary embodiments of apparatus and method for obtaining one or more portions of biological tissue (“micrografts”) to form grafts are provided. For example, a hollow tube can be inserted into tissue at a donor site, and a pin provided within the tube can facilitate controlled removal of the micrograft from the tube. Micrografts can be harvested and directly implanted into an overlying biocompatible matrix through coordinated motion of the tube and pin. A needle can be provided around the tube to facilitate a direct implantation of a micrograft into a remote recipient site or matrix. The exemplary apparatus can include a plurality of such tubes and pins for simultaneous harvesting and/or implanting of a plurality of micrografts. The harvested micrografts can have a small dimension, e.g., less than about 1 mm, which can promote healing of the donor site and/or viability of the harvested tissue.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 5, 2023
    Assignee: The General Hospital Corporation
    Inventors: Richard Rox Anderson, William A. Farinelli, Walfre Franco, Joshua Tam, Fernanda H. Sakamoto, Apostolos G. Doukas, Martin Purschke, Min Yao
  • Publication number: 20230366425
    Abstract: A multi-mount assembly disposed on a fastening structure that has a U-type rail is provided. The multi-mount assembly includes a main body having a quadrilateral rail, a positioning hole, and a passage. The quadrilateral rail is disposed along a periphery of the main body. The positioning hole is in a side of the main body facing away from the fastening structure. The passage is spatially communicated with a first edge and a second edge of the main body, in which the first edge is opposite the second edge. The main body is configured to enter an opening of the U-type rail of the fastening structure such that three sides of the quadrilateral rail are coupled to the U-type rail. The positioning hole is configured to enable a protruding element to pass therethrough.
    Type: Application
    Filed: October 7, 2022
    Publication date: November 16, 2023
    Inventor: Min-Yao FANG
  • Publication number: 20230298986
    Abstract: A package substrate and the manufacturing method thereof are provided. The method includes encapsulating a circuit layer and a conductive pillar on the circuit layer with an insulating layer, and then forming a groove in the insulating layer corresponding to the conductive pillar, so as to form a routing layer in the groove, so there is no need for drilling to make blind vias. Therefore, the alignment problem of conventional circuits and conductive blind vias can be avoided.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 21, 2023
    Inventors: Min-Yao CHEN, Sung-Kun LIN, Andrew C. CHANG
  • Publication number: 20230290744
    Abstract: An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Inventors: Min-Yao CHEN, Andrew C. CHANG