Patents by Inventor Min Yao

Min Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11848296
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
  • Publication number: 20230400648
    Abstract: The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Min-Yao CHENG, Hung-Yi LIN
  • Patent number: 11832845
    Abstract: Exemplary embodiments of apparatus and method for obtaining one or more portions of biological tissue (“micrografts”) to form grafts are provided. For example, a hollow tube can be inserted into tissue at a donor site, and a pin provided within the tube can facilitate controlled removal of the micrograft from the tube. Micrografts can be harvested and directly implanted into an overlying biocompatible matrix through coordinated motion of the tube and pin. A needle can be provided around the tube to facilitate a direct implantation of a micrograft into a remote recipient site or matrix. The exemplary apparatus can include a plurality of such tubes and pins for simultaneous harvesting and/or implanting of a plurality of micrografts. The harvested micrografts can have a small dimension, e.g., less than about 1 mm, which can promote healing of the donor site and/or viability of the harvested tissue.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 5, 2023
    Assignee: The General Hospital Corporation
    Inventors: Richard Rox Anderson, William A. Farinelli, Walfre Franco, Joshua Tam, Fernanda H. Sakamoto, Apostolos G. Doukas, Martin Purschke, Min Yao
  • Publication number: 20230366425
    Abstract: A multi-mount assembly disposed on a fastening structure that has a U-type rail is provided. The multi-mount assembly includes a main body having a quadrilateral rail, a positioning hole, and a passage. The quadrilateral rail is disposed along a periphery of the main body. The positioning hole is in a side of the main body facing away from the fastening structure. The passage is spatially communicated with a first edge and a second edge of the main body, in which the first edge is opposite the second edge. The main body is configured to enter an opening of the U-type rail of the fastening structure such that three sides of the quadrilateral rail are coupled to the U-type rail. The positioning hole is configured to enable a protruding element to pass therethrough.
    Type: Application
    Filed: October 7, 2022
    Publication date: November 16, 2023
    Inventor: Min-Yao FANG
  • Publication number: 20230298986
    Abstract: A package substrate and the manufacturing method thereof are provided. The method includes encapsulating a circuit layer and a conductive pillar on the circuit layer with an insulating layer, and then forming a groove in the insulating layer corresponding to the conductive pillar, so as to form a routing layer in the groove, so there is no need for drilling to make blind vias. Therefore, the alignment problem of conventional circuits and conductive blind vias can be avoided.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 21, 2023
    Inventors: Min-Yao CHEN, Sung-Kun LIN, Andrew C. CHANG
  • Publication number: 20230290744
    Abstract: An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Inventors: Min-Yao CHEN, Andrew C. CHANG
  • Publication number: 20230282556
    Abstract: A substrate structure is provided, in which an insulator encapsulates a conductive pillar that is a single solid pillar body, and at least one wiring layer electrically connected to the conductive pillar is arranged on the insulator. Therefore, the conductive pillar is designed as a single solid pillar body to meet the requirements of thin lines, fine spacing and high-density contacts.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 7, 2023
    Inventors: Min-Yao CHEN, Pei-Ching LI, Andrew C. CHANG
  • Publication number: 20230047153
    Abstract: Face mask including a mask body, lining around an edge of the mask body, and a nose strip, wherein the complete face mask including the mask body, the lining, and the nose strip is made of a single recyclable material, such as PET. The face mask can be ground directly for recycling without first separating the parts of the face mask.
    Type: Application
    Filed: December 2, 2021
    Publication date: February 16, 2023
    Inventors: Min Yao, Roy Yao
  • Publication number: 20220418115
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
  • Patent number: 11492373
    Abstract: A balanced-lattice-ledge nucleant having ledge inducing local densification of proteins and a balanced-lattice inducing self-organized crystal packing. Using this balanced-lattice-ledge nucleant enhances nucleation of protein crystals.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: November 8, 2022
    Assignee: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Min Yao, Long Li
  • Patent number: 11482172
    Abstract: A display device and an operating method of the display device are provided. The display device includes a first light emitting diode (LED), a first switch, a second switch, a second LED, a third switch, and a first controller. A first terminal of the first switch receives a first electrical signal. A first terminal of the second switch receives a second electrical signal. A first terminal of the third switch receives a third electrical signal. Here, whether the first switch, the second switch, and the third switch are switched on or off is determined by whether the first LED and the second LED are damaged or not. The first controller is configured to detect whether the first LED and the second LED are damaged or not, generate the second electrical signal and the electrical signal, and generate a plurality of control signals controlling the first switch to the third switch.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 25, 2022
    Assignee: AU Optronics Corporation
    Inventors: Ming-Chen Hsu, Hsiang-Yuan Hsieh, Min-Yao Lu, Chin-Tang Chuang
  • Publication number: 20220285282
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Min-Yao CHEN
  • Patent number: 11432406
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
  • Patent number: 11342272
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Min-Yao Chen
  • Publication number: 20220157745
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
  • Patent number: 11335650
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 17, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Publication number: 20220095462
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
  • Publication number: 20220052013
    Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Han-Chee YEN, Ying-Nan LIU, Min-Yao CHENG
  • Patent number: 11239184
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Publication number: 20210391284
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN