Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: A memory device receiving a host instruction generated by a host includes a flash memory array and a controller. The controller translates the host instruction into operation instructions, queues the operation instructions in a major command queue, and performs an operation on the flash memory array according to the operation instructions. When an error occurs during execution of the operation commands, the controller performs an error-handling process, queues operation commands related to the error-handling process in an auxiliary command queue, sequentially executes the operation commands in the auxiliary command queue, and stops executing the major command queue.

Abstract: Provided is a method of preparing a powdery diacetal clarifying agent, which comprises mixing an aromatic aldehyde, a polyol, and an acid catalyst in an organic polar solvent, adding a hydrogenating agent and an inorganic silicon-containing agent into the foregoing mixture, and filtering the mixture. The powdery diacetal clarifying agent prepared by the method can have excellent flowability, dispersability, thermal resistance, and color stability. Accordingly, the powdery diacetal clarifying agent does not release stinking odor and incur yellowing at high temperature, allowing the plastic articles to have improved appearance and visual appeal.

Abstract: A storage device receiving an external instruction from a host includes a plurality of flash memory spaces and a controller. The controller receives the external instruction, queues the external instruction in a first command queue, translates the external instruction into a plurality of operation commands, and sequentially executes the operation commands to respectively operate the flash memory spaces. The controller further gives an identity code to at least one specific operation command to track the execution result of the specific operation command.

Abstract: A memory device receiving a host instruction generated by a host includes a flash memory array and a controller. The controller translates the host instruction into operation instructions, queues the operation instructions in a major command queue, and performs an operation on the flash memory array according to the operation instructions. When an error occurs during execution of the operation commands, the controller performs an error-handling process, queues operation commands related to the error-handling process in an auxiliary command queue, sequentially executes the operation commands in the auxiliary command queue, and stops executing the major command queue.

Abstract: Provided are a powdery diacetal clarifying agent and a method of preparing the same. The powdery diacetal clarifying agent comprises a diacetal compound and an inorganic silicon-containing compound having a pH value equal to or more than 6 and equal to or less than 12. The powdery diacetal clarifying agent of the composition can have excellent flowability, dispersability, thermal resistance, and color stability. Accordingly, the powdery diacetal clarifying agent does not release stinking odor and incur yellowing at high temperature, allowing the plastic articles to have improved appearance and visual appeal.

Abstract: Provided is a method of preparing a powdery diacetal clarifying agent, which comprises mixing an aromatic aldehyde, a polyol, and an acid catalyst in an organic polar solvent, adding a hydrogenating agent and an inorganic silicon-containing agent into the foregoing mixture, and filtering the mixture. The powdery diacetal clarifying agent prepared by the method can have excellent flowability, dispersability, thermal resistance, and color stability. Accordingly, the powdery diacetal clarifying agent does not release stinking odor and incur yellowing at high temperature, allowing the plastic articles to have improved appearance and visual appeal.

Abstract: Provided are a powdery diacetal clarifying agent and a method of preparing the same. The powdery diacetal clarifying agent comprises a diacetal compound and an inorganic silicon-containing compound having a pH value equal to or more than 6 and equal to or less than 12. The powdery diacetal clarifying agent of the composition can have excellent flowability, dispersability, thermal resistance, and color stability. Accordingly, the powdery diacetal clarifying agent does not release stinking odor and incur yellowing at high temperature, allowing the plastic articles to have improved appearance and visual appeal.

Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.

Abstract: A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 ?; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer.