Patents by Inventor Ming-Chang Hsieh

Ming-Chang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100013059
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Publication number: 20090313460
    Abstract: The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (1) finding register content of each of the registers in a first cycle and register content of each of the registers in a second cycle, in which the second cycle is next to the first cycle; (2) calculating difference of the register content of each of the registers in the second cycle and the register content of each of the registers in the first cycle; and (3) packing the differences of the register contents into data trace packets, in which the differences of the register contents of adjacent registers are condensed into a single data trace packet when the differences of the register contents of the adjacent registers are zeroes.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 17, 2009
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: CHIH TSUN HUANG, YEN JU HO, MING CHANG HSIEH
  • Patent number: 7183150
    Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: February 27, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chang Hsieh, Hsun-Chih Tsao, Hung-Chih Tsai, Pin-Shyne Chin
  • Publication number: 20050037623
    Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Ming-Chang Hsieh, Hsun-Chih Tsao, Hung-Chih Tsai, Pin-Shyne Chin
  • Patent number: 6815274
    Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: November 9, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co.
    Inventors: Ming-Chang Hsieh, Hsun-Chih Tsao, Hung-Chih Tsai, Pin-Shyne Chin