Patents by Inventor Ming-Che Lee

Ming-Che Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371922
    Abstract: Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20240368863
    Abstract: A bendable positioning structure of an outlet pipe for a faucet contains a body, a spring tube, and a flexible connection tube. The body includes a columnar holder, the outlet pipe, and a fixer. The spring tube is fitted in the outlet pipe and is stopped and positioned by the fixer. The spring tube includes a large-diameter portion and a small-diameter portion which are alternatively formed along the spring tube. The flexible connection tube is slidably received in the spring tube to be limited by the small-diameter portion of the spring tube so that the flexible connection tube is fixed on a centrally-axial line of the output tube. An outer wall of an end of the flexible connection tube is connected with a water head, and the water head is engaged on the outlet pipe and is pulled outward with the flexible connection tube based on user requirements.
    Type: Application
    Filed: May 4, 2023
    Publication date: November 7, 2024
    Inventors: Chin-Tsai Lee, Ming-Che Lee
  • Publication number: 20240371778
    Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ho, Hung-Jui Kuo, Tzung-Hui Lee
  • Publication number: 20240337918
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Application
    Filed: June 20, 2024
    Publication date: October 10, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi TSAI, Wei-Che HSIEH, Ta-Cheng LIEN, Hsin-Chang LEE, Ping-Hsun LIN, Hao-Ping CHENG, Ming-Wei CHEN, Szu-Ping TSAI
  • Patent number: 12094830
    Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Ho, Hung-Jui Kuo, Tzung-Hui Lee
  • Patent number: 12051767
    Abstract: A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The first semiconductor structure includes a first dopant. The second semiconductor structure is located on the first semiconductor structure and includes a second dopant different from the first dopant. The active region includes a plurality of semiconductor pairs and located between the first semiconductor structure and the second semiconductor structure. Each semiconductor pair includes a barrier layer and a well layer and includes the first dopant. The active region does not include a nitrogen element. A doping concentration of the first dopant in the first semiconductor structure is higher than a doping concentration of the first dopant in the active region.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: July 30, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Yen-Chun Tseng, Kuo-Feng Huang, Shih-Chang Lee, Ming-Ta Chin, Shih-Nan Yen, Cheng-Hsing Chiang, Chia-Hung Lin, Cheng-Long Yeh, Yi-Ching Lee, Jui-Che Sung, Shih-Hao Cheng
  • Patent number: 12044959
    Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Yi Tsai, Wei-Che Hsieh, Ta-Cheng Lien, Hsin-Chang Lee, Ping-Hsun Lin, Hao-Ping Cheng, Ming-Wei Chen, Szu-Ping Tsai
  • Patent number: 12003365
    Abstract: A configuration management system tracks the configuration of a managed computing environment in accordance with a configuration tracking policy. The configuration management system uses the tracking policy to map configuration information from the managed computing environment to a hierarchy of configuration items. Items may be included or excluded from the hierarchy based on relevance to the tracking policy and a predicted amount of dynamism. A signature of the hierarchy is generated. A change to the configuration environment is detected based on a change to the signature, and an action is performed in response to the detected change.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 4, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Dallas Lamont Willett, Jeremiah C. Wilton, Mostafa Ead, Ming Che Lee
  • Publication number: 20230411227
    Abstract: Some implementations described herein provide techniques and apparatuses for polishing a perimeter region of a semiconductor substrate so that a roll-off profile at or near the perimeter region of the semiconductor substrate satisfies a threshold. The described implementations include depositing a first layer of a first oxide material across the semiconductor substrate followed by depositing a second layer of a second oxide material over the first layer of the first oxide material and around a perimeter region of the semiconductor substrate. The described implementations further include polishing the second layer of the second oxide material over the perimeter region using a chemical mechanical planarization tool including one or more ring-shaped polishing pads oriented vertically over the perimeter region.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Inventors: I-Nan. CHEN, Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Yung-Lung LIN, Che Wei YANG, Sheng-Chau CHEN
  • Publication number: 20230395640
    Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor. The pixel sensor includes a substrate having a front-side opposite a back-side. An image sensor element comprises an active layer disposed within the substrate, where the active layer comprises germanium. An anti-reflective coating (ARC) structure overlies the back-side of the substrate. The ARC structure includes a first dielectric layer overlying the back-side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first index of refraction of the first dielectric layer is less than a second index of refraction of the second dielectric layer, and a third index of refraction of the third dielectric layer is less than the first index of refraction.
    Type: Application
    Filed: August 4, 2023
    Publication date: December 7, 2023
    Inventors: Cheng-Hsien Chou, Sheng-Chau Chen, Ming-Che Lee
  • Patent number: 11832380
    Abstract: A fan structure automatically mountable on a system circuit board includes a fan. The fan includes a fan frame main body. A connector connection section is disposed on the fan frame main body for connecting with a fan end connector, whereby the fan end connector can be assembled with the fan frame main body. Accordingly, when the fan is mounted on the system circuit board, the fan end connector can be directly pressed down by means of an automated device to plug into the circuit board end connector. Therefore, the manufacturing process can be automated.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: November 28, 2023
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Sung-Wei Sun, Ming-Che Lee
  • Publication number: 20230373018
    Abstract: In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 23, 2023
    Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Ping-Tzu Chen
  • Patent number: 11814825
    Abstract: A telescopic structure of a faucet having a movable tube contains: a body, a water supply tube, a movable tube, a spring, and a depressurization element. The body includes a screwing portion, a coupling portion, and a water outlet. The water supply includes an upright extension and an opening. The movable tube includes a slide portion and a water head engaged with the opening of the water supply tube and is pulled with the movable tube based on using requirements. The spring is accommodated in the upright extension and is fitted on the movable tube. The depressurization element includes a first face, a second face opposite to the first face, a peripheral face defined between and connected with the first face and the second face, and multiple flowing apertures defined proximate to a center of the depressurization element and communicating with the first face and the second face.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: November 14, 2023
    Assignee: Ching Shenger Co., Ltd.
    Inventors: Chin-Tsai Lee, Ming-Che Lee
  • Patent number: 11799221
    Abstract: A fan connector structure is applicable to a system circuit board having a circuit board-end connector provided thereon and includes a fan having a fan frame main body and a fan-end connector projected from an outer side of the fan frame main body. The fan-end connector and the fan frame main body can be selectively integrally or non-integrally formed with each other. The fan-end connector is correspondingly connectable to the circuit board-end connector, so as to realize the purpose of automated and quick assembling of the fan to the system circuit board with less labor and time cost.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 24, 2023
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Sung-Wei Sun, Ming-Che Lee
  • Publication number: 20230187294
    Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 15, 2023
    Inventors: Ming-Che Lee, Kuo-Ming Wu, Sheng-Chau Chen, Hau-Yi Hsiao, Guanyu Luo, Ping-Tzu Chen, Cheng-Yuan Tsai
  • Patent number: 11670539
    Abstract: A method of making a semiconductor arrangement includes forming a first layer of molecular ions in a first wafer interface region of a first wafer, forming a second layer of molecular ions in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 11664411
    Abstract: A semiconductor structure includes: a substrate; a first passivation layer over the substrate; a second passivation layer over the first passivation layer; and a magnetic core in the second passivation layer, wherein the magnetic core includes a first magnetic material layer and a second magnetic material layer over the first magnetic material layer, the first magnetic material layer and the second magnetic material layer are separated by a high resistance isolation layer, and the high resistance isolation layer has a resistivity greater than about 1.3 ohm-cm.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, I-Nan Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Publication number: 20230129760
    Abstract: A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
    Type: Application
    Filed: December 23, 2022
    Publication date: April 27, 2023
    Inventors: Kuo-Ming WU, Ming-Che LEE, Hau-Yi HSIAO, Cheng-Hsien CHOU, Sheng-Chau CHEN, Cheng-Yuan TSAI
  • Patent number: 11618114
    Abstract: A spindle device is mountable with a tool holder, and includes a rotating spindle rotatably mounted to a spindle main body and extending axially to have an axial end surface. A contactless power transmission module is disposed on a flange end surface of the spindle main body and an outer peripheral wall of the rotating spindle for supplying power. An electrically connecting module includes two conductive units each disposed in the rotating spindle and electrically connected with the power transmission module. Each conductive unit has an electrically conductive post extending axially and exposed from the axial end surface for conducting the power to the tool holder.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 4, 2023
    Assignee: ANDERSON INDUSTRIAL CORP.
    Inventors: Yao-Hui Chen, Yu-Shih Chen, Ming-Che Lee
  • Publication number: 20230061299
    Abstract: A fan connector structure is applicable to a system circuit board having a circuit board-end connector provided thereon and includes a fan having a fan frame main body and a fan-end connector projected from an outer side of the fan frame main body. The fan-end connector and the fan frame main body can be selectively integrally or non-integrally formed with each other. The fan-end connector is correspondingly connectable to the circuit board-end connector, so as to realize the purpose of automated and quick assembling of the fan to the system circuit board with less labor and time cost.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: Sung-Wei Sun, Ming-Che Lee