Ming Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A liquid cooling device includes a base (1), a passive impeller (3) and a cold plate (4). The base (1) includes a division plate (11), a chamber (12) and a flow guiding pole (13). The division plate (11) divides the chamber (12) into a catchment portion and a heat exchanging portion (17). The flow guiding pole (13) communicates with both the catchment portion (16) and the heat exchanging portion (17). The passive impeller (3) is received in the chamber (12) and radially driven to rotate by the working fluid. The cold plate (4) is arranged correspondingly to the heat exchanging portion (17) and fastened to the base (1).
Abstract: A method for forming a semiconductor arrangement includes forming a fin. A diffusion process is performed to diffuse a first dopant into the channel region of the fin. A first gate electrode is formed over the channel region of the fin after the first dopant is diffused into the channel region of the fin.
Abstract: The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting light omni-directionally. Wherein the LED chip is disposed on one surface of the substrate and the light emitting angle of the LED chip is wider than 180°, and the light emitted by the LED chip will penetrate into the substrate and at least partially emerge from another surface of the substrate. According to the present invention, the light emitting device using LED chips can provide sufficient lighting intensity and uniform lighting performance.
Abstract: The disclosure provides a manufacturing method of an LED display device, including the following steps: providing a substrate; forming at least one first bonding pad and at least one second bonding pad on the substrate; forming at least one spacer on the substrate, wherein the spacer is located between the first bonding pad and the second bonding pad, and a height of the spacer is P ?m; providing a conductive paste layer above the substrate, wherein the conductive paste layer includes a plurality of conductive particles; and bonding at least one LED on the substrate, wherein the LED includes a first electrode and a second electrode, and the first electrode and the second electrode have a height H ?m. The first electrode and the second electrode of the LED are respectively electrically connected to the first bonding pad and the second bonding pad of the substrate through the conductive particles of the conductive paste layer, and H+3.5 ?m?P ?m?H+0.48 ?M.
Abstract: The present invention provides a hearing protection earphone, a hearing protection method and a computer program storage medium, comprising a sound control system including a wearing-status sensing module for monitoring a current wearing status of the hearing protection earphone, sending a first monitoring signal when it is determined that the hearing protection earphone is in a wearing state, and sending a second monitoring signal when it is determined that the hearing protection earphone is in a non-wearing state; and a main control module for enabling a play function corresponding to a play mode which is adapted to the hearing protection earphone currently when the first monitoring signal sent from the wearing-status sensing module is received, and counting a stand-by time of the protection earphone and turning off the hearing protection earphone after a preset stand-by time elapses when the second monitoring signal sent from the wearing-status sensing module is received.
Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.
Abstract: A method for PDCCH monitoring performed by a UE is provided. The method includes receiving, from a base station, a first PDCCH monitoring configuration and a second PDCCH monitoring configuration, where the second PDCCH monitoring configuration allocates a plurality of PDCCH monitoring occasions within a slot. The method also includes performing PDCCH monitoring based on at least one of the first PDCCH monitoring configuration and the second PDCCH monitoring configuration. The maximum number of non-overlapped CCEs in one slot is bound by a slot CCE limit. The slot CCE limit of the first PDCCH monitoring configuration is different from the slot CCE limit of the second PDCCH monitoring configuration.
Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.
January 31, 2020
May 28, 2020
Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
Abstract: A traffic controller includes a controller configured to reject a request and issue a speed requirement based on a priority to cause a speed of a one of a plurality of vehicles to be within a speed band before entering a road. The rejection is responsive to receiving the speed request from the one approaching the road having priority less than a predetermined threshold and outside of a speed band and a predetermined acceleration band of vehicles on the road.
November 26, 2018
May 28, 2020
Yanan ZHAO, Ming CHENG, Girish Gokul CHENNUPALLI, Alex SZCZEPANIAK, Mark Steven YAMAZAKI
Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.
Abstract: A drive circuit for driving a display panel includes a dynamic refresh unit, a timer, and a black insertion drive unit. The dynamic refresh unit is configured to output a dynamic refresh signal, so as to control the display panel to display a plurality of frames in sequence. A frame time of each of the frames is adjusted according to the dynamic refresh signal. The timer is configured to compute a black insertion time signal. The black insertion drive unit is configured to output a black insertion drive signal according to the black insertion time signal, so as to perform black insertion on the frames.
Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.
Abstract: A method for performing DBO measurements utilizing apertures having a single pole includes using a first aperture plate to measure X-axis diffraction of a composite grating. In some embodiments, the first aperture plate has a first pair of radiation-transmitting regions disposed along a first diametrical axis and on opposite sides of an optical axis that is aligned with a center of the first aperture plate. Thereafter, in some embodiments, a second aperture plate, which is complementary to the first aperture plate, is used to measure Y-axis diffraction of the composite grating. By way of example, the second aperture plate has a second pair of radiation-transmitting regions disposed along a second diametrical axis and on opposite sides of the optical axis. In some cases, the second diametrical axis is substantially perpendicular to the first diametrical axis.
Abstract: A method, apparatus, and electronic device for voice navigation are disclosed. A voice input mechanism 310 may receive a verbal input from a user to a voice user interface program invisible to the user. A processor 104 may identify in a graphical user interface (GUI) a set of GUI items. The processor 104 may convert the set of GUI items to a set of voice searchable indices 400. The processor 104 may correlate a matching GUI item of the set of GUI items to a phonemic representation of the verbal input.
August 20, 2014
Date of Patent:
May 26, 2020
Yan Ming Cheng, Changxue Ma, Theodore Mazurkiewicz
Abstract: A driving circuit includes a first driving switch, a second driving switch and a current regulating unit. The first driving switch is electrically connected to a first power source and a first light emitting element. When the first driving switch is turned on, the first driving switch is configured to receive a first current. The second driving switch is electrically connected to a second power source and a second light emitting element. When the second driving switch is turned on, the second driving switch is configured to receive a second current. The current regulating unit is electrically connected to a negative terminal of the second light emitting element and a positive terminal of the first light emitting element. When the current regulating unit is disabled, the second current sequentially flows through the second light emitting element and the first light emitting element.
Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes first fins, second fins, a first gate strip, a second gate strip and a comb-like insulating structure. The first and second fins are disposed on a substrate. The first gate strip is disposed across the first fins. The second gate strip is disposed across the second fins. The comb-like insulating structure is disposed between the first gate strip and the second gate strip and has a plurality of comb tooth parts. In some embodiments, each of the comb tooth parts has a middle-wide profile.
Abstract: A user equipment (UE) is configured with at least one bandwidth part (BWP) specific configuration information. The UE receives a configuration information specific to the bandwidth part (BWP). The configuration information configures an initial value of a beam failure detection (BFD) timer and a beam failure indication (BFI) count threshold. The UE starts or re-starts the BFD timer from the initial value when receiving a beam failure indication (BFI) from a lower sublayer, and counts a number of the received BFIs using a BFI counter. The UE resets the BFI counter to zero when receiving a reconfiguration information. The reconfiguration information, that is specific to the BWP, re-configures at least one of the initial value of the BFD timer and the BFI count threshold.
Abstract: A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.
Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.