Patents by Inventor Ming-Chiang Lee

Ming-Chiang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8510940
    Abstract: A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: August 20, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Min-Yao Chen, Mao-Chang Chuang, Ming-Chiang Lee, Chien-Hao Wang
  • Patent number: 8497585
    Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 30, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ming-Chiang Lee
  • Patent number: 8487426
    Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 16, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kay Stephan Essig, Bernd Karl Appelt, Ming Chiang Lee
  • Patent number: 8416577
    Abstract: The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: April 9, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hao Wang, Ming-Chiang Lee
  • Patent number: 8387239
    Abstract: An embedded circuit substrate comprising: a core structure having a first surface and a second surface opposite to each other; a first patterned conductive layer disposed on the first surface and embedded in the core structure; a second patterned conductive layer disposed on the second surface and embedded in the core structure; and a plurality of conductive blocks disposed in the core structure for conducting the first patterned conductive layer and the second patterned conductive layer is provided. Furthermore, a manufacturing method of an embedded circuit substrate is also provided.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: March 5, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Hao Wang, Ming-Chiang Lee
  • Patent number: 8372689
    Abstract: In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: February 12, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Chiang Lee, Chien-Hao Wang
  • Patent number: 8320134
    Abstract: An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: November 27, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Ming-Chiang Lee, Chien-Hao Wang
  • Patent number: 8288869
    Abstract: A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming-Chiang Lee, Bernd Karl Appelt, Chia-Hsiung Hsieh
  • Patent number: 8284561
    Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: October 9, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt, Ming-Chiang Lee
  • Publication number: 20120235309
    Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kay Stephan Essig, Bernd Karl Appelt, Ming Chiang Lee
  • Publication number: 20120153493
    Abstract: An embedded component device includes an electronic component including an electrical contact, an upper patterned conductive layer, a dielectric layer between the upper patterned conductive layer and the electronic component, a first electrical interconnect, a lower patterned conductive layer, a conductive via, and a second electrical interconnect. The dielectric layer has a first opening exposing the electrical contact, and a second opening extending from the lower patterned conductive layer to the upper patterned conductive layer. The first electrical interconnect extends from the electrical contact to the upper patterned conductive layer, and fills the first opening. The second opening has an upper portion exposing the upper patterned conductive layer and a lower portion exposing the lower patterned conductive layer. The conductive via is located at the lower portion of the second opening. The second electrical interconnect fills the upper portion of the second opening.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: CHUN-CHE LEE, YUAN-CHANG SU, MING CHIANG LEE, SHIH-FU HUANG
  • Publication number: 20120073871
    Abstract: The present invention directs to double-sided multi-layered substrate a base, at least a through-hole passing through the base, patterned first and second metal layers formed on the two opposite surfaces of the base, and first and second plating layers. The first plating layer covers a sidewall of the through-hole and the bottom surface surrounding a bottom opening of the through hole. The second plating layer covers the first plating layer and the top surface surrounding a top opening of the through hole.
    Type: Application
    Filed: November 30, 2011
    Publication date: March 29, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Yuan-Chang Su, Ming-Chiang Lee, You-Lung Yen
  • Publication number: 20120033394
    Abstract: The present invention directs to fabrication methods of the embedded component package structures by providing preformed lamination structures, joining or stacking the preformed laminate structures and mounting at least one electronic component to the joined structures. By way of the fabrication methods, the production yield can be greatly improved with lower cycle time.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Bernd Karl Appelt, Ming-Chiang Lee
  • Patent number: 8104171
    Abstract: The present invention directs to fabrication methods of single-sided or double-sided multi-layered substrate by providing a lamination structure having at least a core structure and first and second laminate structures stacked over both surfaces of the core structure. The core structure functions as the temporary carrier for carrying the first and second laminate structures through the double-sided processing procedures. By way of the fabrication methods, the production yield can be greatly improved without increasing the production costs.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: January 31, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl Appelt, Yuan-Chang Su, Ming-Chiang Lee, You-Lung Yen
  • Patent number: 8059422
    Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: November 15, 2011
    Assignees: Advanced Semiconductor Engineering, Inc., ASE Electronics Inc.
    Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen
  • Publication number: 20110260327
    Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
    Type: Application
    Filed: June 30, 2011
    Publication date: October 27, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ming-Chiang Lee
  • Publication number: 20110194265
    Abstract: An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.
    Type: Application
    Filed: February 5, 2010
    Publication date: August 11, 2011
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Ming-Chiang Lee, Chien-Hao Wang
  • Patent number: 7993982
    Abstract: A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: August 9, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Ming-Chiang Lee
  • Publication number: 20110174529
    Abstract: A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.
    Type: Application
    Filed: May 28, 2010
    Publication date: July 21, 2011
    Inventors: Min-Yao CHEN, Mao-Chang Chuang, Ming-Chiang Lee, Chien-Hao Wang
  • Publication number: 20110177654
    Abstract: In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Inventors: Ming-Chiang Lee, Chien-Hao Wang