Abstract: A video processing apparatus includes: a line-based data encoder for performing line-based data encoding on an input signal to generate a line-based data encoded signal; and a video signal controller coupled to the line-based data encoder for receiving a first video signal and the line-based data encoded signal, decoding the line-based data encoded signal to generate a second video signal, and choosing one of the first and second video signals to generate an output signal.

Abstract: A visual effect generating module for changing visual effects of a selected image block within an image area is disclosed. The visual effect generating module includes a color changing module for receiving and changing pixel values of a plurality of pixels within the selected image block and a first multiplexer coupled to the color changing module for selectively outputting pixels corresponding to the image area or pixels output from the color changing module.

Abstract: A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.

Abstract: A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.

Abstract: The apparatus for inhibiting the ring back effect of a circuit comprises a first differential current mode pair and a second differential current mode pair. The first differential current mode pair outputs a first current and a second current through the controlling of a first control signal. The second differential current mode pair outputs a third current and a fourth current through the controlling of a second control signal. The second control signal is the delayed first control signal. The first current and the third current are combined to be the first output current signal, while the second current and the fourth current are combined to be the second output current signal. The magnitude and time delay of the third and fourth currents are designed to compensate the first and second currents respectively so as to inhibit the ring back effect.