Patents by Inventor Ming-Chyi Liu

Ming-Chyi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028985
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Application
    Filed: October 12, 2021
    Publication date: January 27, 2022
    Inventors: SHENG-CHIEH CHEN, MING CHYI LIU, SHIH-CHANG LIU
  • Patent number: 11226506
    Abstract: In some embodiments, the present disclosure relates to a modulator device that includes an input terminal configured to receive impingent light. A first waveguide has a first output region and a first input region that is coupled to the input terminal. A second waveguide is optically coupled to the first waveguide and has second input region and a second output region that is coupled to the input terminal. An output terminal coupled to the first output region of the first waveguide and the second output region of the second waveguide is configured to provide outgoing light that is modulated. A heater structure is configured to provide heat to the first waveguide to induce a temperature difference between the first and second waveguides. A gas-filled isolation structure is proximate to the heater structure and is configured to thermally isolate the second waveguide from the heat provided to the first waveguide.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Lin, Ming Chyi Liu
  • Publication number: 20220013482
    Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.
    Type: Application
    Filed: November 20, 2020
    Publication date: January 13, 2022
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 11222896
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11217596
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11211469
    Abstract: A memory device and method of making the same are disclosed. The memory device includes a first split gate memory cell including a first memory stack located over a substrate. The first memory stack includes a first floating gate and a first control gate located above the first floating gate. The split gate memory cell also includes a first select gate located adjacent to the first floating gate and the first control gate and a contact etch stop located over a portion of a top surface of the first select gate. The contact etch stop enables a narrowing of the drain contact via during an etch process. By narrowing the drain contact via, the density of split gate memory cells may be increased.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Patent number: 11209673
    Abstract: Various embodiments of the present disclosure are directed towards a modulator device including a first waveguide and a heater structure. An input terminal is configured to receive impingent light. The first waveguide has a first output region and a first input region coupled to the input terminal. A second waveguide is optically coupled to the first waveguide. The second waveguide has a second output region and a second input region coupled to the input terminal. An output terminal is configured to provide outgoing light that is modulated based on the impingent light. The output terminal is coupled to the first output region and the second output region. The heater structure overlies the first waveguide. A bottom surface of the heater structure is aligned with a bottom surface of the first waveguide. The first waveguide is spaced laterally between sidewalls of the heater structure.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Lin, Ming Chyi Liu
  • Publication number: 20210384211
    Abstract: The present disclosure relates to a method of forming a flash memory structure. The method includes forming a sacrificial material over a substrate, and forming a plurality of trenches extending through the sacrificial material to within the substrate. A dielectric material is formed within the plurality of trenches. The dielectric material is selectively etched, according to a mask that is directly over the dielectric material, to form depressions along edges of the plurality of trenches. The sacrificial material between neighboring ones of the depressions is removed to form a floating gate recess. A floating gate material is formed within the floating gate recess and the neighboring ones of the depressions.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Inventors: Hung-Shu Huang, Ming Chyi Liu
  • Publication number: 20210376120
    Abstract: A memory device and method of making the same are disclosed. The memory device includes a first split gate memory cell including a first memory stack located over a substrate. The first memory stack includes a first floating gate and a first control gate located above the first floating gate. The split gate memory cell also includes a first select gate located adjacent to the first floating gate and the first control gate and a contact etch stop located over a portion of a top surface of the first select gate. The contact etch stop enables a narrowing of the drain contact via during an etch process. By narrowing the drain contact via, the density of split gate memory cells may be increased.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Inventors: Jhih-Bin CHEN, Ming Chyi LIU
  • Publication number: 20210376282
    Abstract: In some embodiments, the present disclosure relates to a display device that includes a first reflector electrode and a second reflector electrode that is separated from the first reflector electrode. The display device further includes an isolation structure that overlies the first and second reflector electrodes. The isolation structure includes a first and second portion. The first portion overlies the first reflector electrode and has a first thickness. The second portion overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure. The display device also includes a first optical emitter structure and a second optical emitter structure that respectively overlie the first portion and the second portion of the isolation structure.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Yung-Chang Chang, Ming Chyi Liu
  • Patent number: 11183571
    Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yong-Sheng Huang, Ming-Chyi Liu, Chih-Ren Hsieh
  • Patent number: 11171147
    Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Chen, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11164844
    Abstract: In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen Yu Chen, Ming Chyi Liu, Eugene Chen
  • Patent number: 11158797
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11158789
    Abstract: In some methods, a contact is formed over a substrate, and a bottom electrode layer is formed over the contact. A first dielectric layer is formed to cover a peripheral portion of the bottom electrode layer but not a central portion of the bottom electrode layer. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer includes a central dielectric region that contacts the central portion of the bottom electrode layer, and a peripheral dielectric region over the peripheral portion of the bottom electrode. A step dielectric region connects the central and peripheral dielectric regions. A top electrode layer is formed over the second dielectric layer. The top electrode layer includes a central top electrode region, a peripheral top electrode region, and a step top electrode region directly above the central dielectric region, the peripheral dielectric region, and the step dielectric region, respectively.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11158648
    Abstract: A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 11158593
    Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Bin Chen, Chia-Shiung Tsai, Ming Chyi Liu, Eugene Chen
  • Publication number: 20210328174
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming an isolation structure over a reflector electrode and forming a protective layer over the isolation structure. Further, a first removal process is performed to form a first opening in the protective layer and the isolation structure to expose a first surface of the reflector electrode. A cleaning process is performed to clean the first surface of the reflector electrode. A conductive layer is formed over the protective layer and within the first opening. The conductive layer includes a different material than the protective layer. A second removal process is performed to remove peripheral portions of the protective layer and the conductive layer to form a via structure within the opening, extending through the isolation structure to contact the reflector electrode, and including the protective layer and the conductive layer.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Inventors: Yung-Chang Chang, Ming Chyi Liu
  • Patent number: 11152384
    Abstract: An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Chyi Liu, Shih-Chang Liu
  • Patent number: 11143817
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate and a gate element over the substrate. The gate element includes: a gate dielectric layer over the substrate; a gate electrode over the gate dielectric layer; and a waveguide passing through the gate electrode from a top surface of the gate electrode to a bottom surface of the gate electrode. A manufacturing method of the same is also disclosed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Chang Chang, Chung-Yen Chou, Ming-Chyi Liu, Shih-Chang Liu