Abstract: The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: The present disclosure relates to an image sensor. The image sensor includes a substrate and a photodetector in the substrate. The image sensor further includes an absorption enhancement structure. The absorption enhancement structure is defined by a substrate depression along a first side of the substrate. The substrate depression is defined by a first plurality of sidewalls that slope toward a first common point and by a second plurality of sidewalls that slope toward a second common point. The first plurality of sidewalls extend over the second plurality of sidewalls.

Abstract: A semiconductor device is provided. The semiconductor device includes a silicon nitride waveguide in a first dielectric layer over a substrate. The semiconductor device includes a semiconductor waveguide in a second dielectric layer over the first dielectric layer. The first dielectric layer including the silicon nitride waveguide is between the second dielectric layer including the semiconductor waveguide and the substrate.

Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

Abstract: In some embodiments, the present disclosure relates to a display device that includes an isolation structure disposed over a reflector electrode, a transparent electrode disposed over the isolation structure, an optical emitter structure disposed over the transparent electrode, and a via structure. The via structure extends from the transparent electrode at a top surface of the isolation structure to a top surface of the reflector electrode. The via structure includes a center horizontal segment that contacts the top surface of the reflector electrode, a sidewall vertical segment that contacts an inner sidewall of the isolation structure, and an upper horizontal segment that is connected to the center horizontal segment by the sidewall vertical segment. The upper horizontal segment is thicker than the center horizontal segment.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate dielectric, a gate electrode, a field plate dielectric layer, and a field plate. The gate dielectric layer is arranged over a substrate and between a source region and a drain region. The gate electrode is arranged over the gate dielectric layer. The field plate dielectric layer is arranged over the substrate and between the gate dielectric layer and the drain region.

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

Abstract: Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.

Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

Abstract: Various embodiments of the present disclosure are directed towards a modulator device including a first waveguide and a heater structure. An input terminal is configured to receive impingent light. The first waveguide has a first output region and a first input region coupled to the input terminal. A second waveguide is optically coupled to the first waveguide. The second waveguide has a second output region and a second input region coupled to the input terminal. An output terminal is configured to provide outgoing light that is modulated based on the impingent light. The output terminal is coupled to the first output region and the second output region. The heater structure overlies the first waveguide. A bottom surface of the heater structure is aligned with a bottom surface of the first waveguide. The first waveguide is spaced laterally between sidewalls of the heater structure.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: In some embodiments, the present disclosure relates to a display device that includes an isolation structure disposed over a reflector electrode, a transparent electrode disposed over the isolation structure, an optical emitter structure disposed over the transparent electrode, and a via structure. The via structure extends from the transparent electrode at a top surface of the isolation structure to a top surface of the reflector electrode. The via structure includes a center horizontal segment that contacts the top surface of the reflector electrode, a sidewall vertical segment that contacts an inner sidewall of the isolation structure, and an upper horizontal segment that is connected to the center horizontal segment by the sidewall vertical segment. The upper horizontal segment is thicker than the center horizontal segment.

Abstract: In some embodiments, the present disclosure relates to a vertical cavity surface emitting laser (VCSEL) device that includes a microlens arranged over a reflector stack. The reflector stack comprises alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer comprises a first average concentration of a first element and has a first width. The second lens layer comprises a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer comprises a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.

Abstract: In some embodiments, the present disclosure relates to a method of forming a package assembly. A wet etch stop layer is formed over a frontside of a semiconductor substrate. A sacrificial semiconductor layer is formed over the wet etch stop layer, and a dry etch stop layer is formed over the sacrificial semiconductor layer. A stack of semiconductor device layers may be formed over the dry etch stop layer. A bonding process is performed to bond the stack of semiconductor device layers to a frontside of an integrated circuit die, wherein the frontside of the semiconductor substrate faces the frontside of the integrated circuit die. A wet etching process is performed to remove the semiconductor substrate, and a dry etching process is performed to remove the wet etch stop layer and the sacrificial semiconductor layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.