Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Abstract: A semiconductor device includes a metallic pattern provided above a substrate and extending in a first direction with a first width, a first active metallic feature directly connected to the metallic pattern and extending in a second direction from the metallic pattern with a second width that is smaller than the first width, and a first dummy metallic feature arranged adjacently to the first active metallic feature. The first dummy metallic feature is directly connected to the metallic pattern and extends in the second direction from the metallic pattern while not electrically connected to lines other than the metallic pattern.

Abstract: Optical devices and methods of manufacture are presented in a first optical package is received, the first optical package including a first positioning opening and a receptacle opening. A receptacle is inserted into the receptacle opening and the first positioning opening in order to access an edge coupler within the first optical package.

Abstract: A method of manufacturing an optical device that can include forming a plurality of first metal structures on a first region of a base surface of a die and a second metal structure on a second region of the base surface of the die, wherein the second metal structure has a different shape compared to the at least the first metal structure, and the second metal structure has a bar-type shape. The method can further include bonding the die to a supporting substrate through the plurality of the first metal structures, and applying an underfill material between the base surface of the die and the supporting substrate. In some embodiments, in a cross-sectional view, the underfill material extends from a top surface of the supporting substrate to a sidewall of the die.

Abstract: Optical devices and methods of manufacture are presented in which a fiber array unit is connected to a first optical package. In embodiments the fiber array unit is passively aligned using a first projection and an opening and then actively aligned after being passively aligned. Once aligned, the fiber array unit is adhered using an adhesive.

Abstract: A semiconductor structure includes a photonic die and a conductive connector. The photonic die includes: an insulating layer having a first side and a second side; at least one optical element disposed on the first side of the insulating layer; a through via penetrating through the insulating layer and aside the at least one optical element, and having a metal is in direct contact with the insulating layer; and an interconnect structure disposed over the first side of the insulating layer and electrically connected to the through via. The conductive connector is disposed on the second side of the insulating layer and electrically connected to the through via. A critical dimension of the through via is between a critical dimension of the interconnect structure and a critical dimension of the conductive connector.

Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

Abstract: A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

Abstract: A semiconductor package includes a semiconductor die, a device layer over the semiconductor die and including an optical device, an insulator layer over the device layer, a buffer layer over the insulator layer, an etch stop layer between the device layer and the insulator layer, a connective terminal, and a bonding via passing through the device layer and electrically connecting the semiconductor die to the connective terminal. The conductive terminal passes through the etch stop layer, the insulator layer, and the buffer layer. The conductive terminal is in direct contact with the etch stop layer.

Abstract: A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.

Abstract: A semiconductor device includes a photonic die and a reflector coupler. The photonic die includes an edge coupler. At least a portion of the reflector coupler is disposed outside the photonic die. A light from the edge coupler is reflected by the reflector coupler, or a light is reflected by the reflector coupler and then incident into the edge coupler.

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.

Abstract: A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a semiconductor substrate and a second bonding structure over the semiconductor substrate. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. Sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate. The first connectors are in physical contact with the second connectors. The first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer. The encapsulant laterally encapsulates the second die. The TIVs are aside the second die.

Abstract: Optical devices and methods of manufacture are presented in which a metasurface is utilized to assist optical signals as the optical signals transit between an external device such as an optical fiber and an edge coupler located within a first optical package. The metasurface includes meta-atoms which may be used to help lead the optical signals to the edge coupler.

Abstract: A semiconductor package includes a photonic die including an optical coupler, an electronic die bonded over the photonic die, and a optical support bonded over the electronic die and includes a plurality of lens structures, wherein light from an external optical signal source is coupled to the optical coupler sequentially through the plurality of lens structures.

Abstract: A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.

Abstract: A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed opposite the first and second device features from the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Abstract: A sacrificial component over a first side of a substrate. The sacrificial component has a curved profile. First etching processes are performed to the sacrificial component and the substrate from the first side, which remove the sacrificial component and defines a first portion of the substrate below the sacrificial component as a microlens. The microlens has a second curved profile. A mask layer is formed over the first side of the substrate to surround the microlens. The mask layer and the substrate have different material compositions. Second etching processes are performed to the mask layer and the substrate from the first side. The mask layer is etched at a slower rate than the substrate, such that the microlens has a smaller height than a second portion of the substrate below the mask layer after the second etching processes have been completed. The mask layer is then removed.