Patents by Inventor Ming-Fa Chen

Ming-Fa Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11372160
    Abstract: A package includes a photonic integrated circuit die, an electric integrated circuit die, and an encapsulant. The photonic integrated circuit die includes a semiconductor substrate, an insulation layer, and a waveguide. The semiconductor substrate has a notch. The insulation layer is disposed on the semiconductor substrate. The waveguide is disposed on the insulation layer. The notch of the semiconductor substrate is underneath at least a portion of the waveguide. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The encapsulant laterally encapsulates the electric integrated circuit die.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11373953
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first portion includes forming a first patterned conductive pad with a first through hole on a first interconnect structure over a first semiconductor substrate; patterning a dielectric material over the first interconnect structure to form a first patterned dielectric layer with a first opening that passes through a portion of the dielectric material formed inside the first through hole to accessibly expose the first interconnect structure; and forming a conductive material inside the first opening and in contact with the first interconnect structure to form a first conductive connector laterally isolated from the first patterned conductive pad by the first patterned dielectric layer. A singulation process is performed to cut off the first patterned dielectric layer, the first interconnect structure, and the first semiconductor substrate to form a continuous sidewall of a semiconductor structure.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11373981
    Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Jian-Wei Hong
  • Publication number: 20220196479
    Abstract: A microelectromechanical infrared sensing device is provided, which includes a substrate, a sensing plate, a reflecting plate, a plurality of first supporting elements, a plurality of second supporting elements and a plurality of stoppers. The second supporting elements are connected to the sensing plate, such that the sensing plate is suspended above the substrate. The reflecting plate is disposed between the substrate and the sensing plate. The first supporting elements are connected to the reflecting plate, such that the reflecting plate is suspended between the substrate and the reflecting plate. When the reflecting plate moves toward the substrate and at least one of the stoppers contacts the substrate or the reflecting plate, the distance between the reflecting plate and the sensing plate increases.
    Type: Application
    Filed: April 26, 2021
    Publication date: June 23, 2022
    Inventors: BOR-SHIUN LEE, MING-FA CHEN
  • Patent number: 11366015
    Abstract: A microelectromechanical infrared sensing device is provided, which includes a substrate, a sensing plate, a reflecting plate, a plurality of first supporting elements, a plurality of second supporting elements and a plurality of stoppers. The second supporting elements are connected to the sensing plate, such that the sensing plate is suspended above the substrate. The reflecting plate is disposed between the substrate and the sensing plate. The first supporting elements are connected to the reflecting plate, such that the reflecting plate is suspended between the substrate and the reflecting plate. When the reflecting plate moves toward the substrate and at least one of the stoppers contacts the substrate or the reflecting plate, the distance between the reflecting plate and the sensing plate increases.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: June 21, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bor-Shiun Lee, Ming-Fa Chen
  • Publication number: 20220189918
    Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11359970
    Abstract: A microelectromechanical infrared sensing apparatus includes a substrate, a sensing plate, a plurality of supporting elements and a plurality of stoppers. The substrate includes an infrared reflecting layer. The sensing plate includes an infrared absorbing layer. The supporting elements are disposed on the substrate, and each of the supporting elements is connected to the sensing plate, such that the sensing plate is suspended above the infrared reflecting layer. The stoppers are disposed between the substrate and the sensing plate. When the sensing plate moves toward the infrared reflecting layer and the stoppers contact both the substrate and the sensing plate, the distance between the sensing plate and the infrared reflecting layer is substantially equal to the height of at least one of the stoppers.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 14, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Bor-Shiun Lee, Ming-Fa Chen, Ying-Che Lo, Chao-Ta Huang
  • Patent number: 11362065
    Abstract: A package includes a first die, a second die, an encapsulant, and a redistribution structure. The first die has a first capacitor embedded therein. The second die has a second capacitor embedded therein. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die. The redistribution structure is disposed on the second die and the encapsulant.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11362064
    Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen, Sung-Feng Yeh, Ying-Ju Chen
  • Patent number: 11362066
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, a second semiconductor die, an insulating layer, and a first dual-damascene connector electrically connected to the first semiconductor die. The first semiconductor die includes a first bonding surface including a die attaching region and a peripheral region connected to the die attaching region. The second semiconductor die is electrically connected to the first semiconductor die, and a second bonding surface of the second semiconductor die is bonded to the first bonding surface in the die attaching region. The insulating layer disposed on the first bonding surface in the peripheral region extends along sidewalls of the second semiconductor die. The first dual-damascene connector includes a first portion disposed on the insulating layer, and a second portion penetrating through the insulating layer and landing on the first bonding surface in the peripheral region.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11362069
    Abstract: A stacking structure including a first die, a second die stacked on the first die, and a filling material is provided. The first die has a first bonding structure, and the first bonding structure includes first bonding pads and a first heat dissipating element. The second die has a second bonding structure, and the second bonding structure includes second bonding pads and a second heat dissipating element. The first bonding pads are bonded with the second bonding pads. The first heat dissipating element is connected to one first bonding pad of the first bonding pads and the second heat dissipating element is connected to one second bonding pad of the second bonding pads. The filling material is disposed over the first die and laterally around the second die. The first and second dies are bonded through the first and second bonding structures.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Publication number: 20220181301
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20220173059
    Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Hsien-Wei Chen, Jie Chen
  • Publication number: 20220173070
    Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11347001
    Abstract: A structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. The electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. The waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. The insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: May 31, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20220165633
    Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.
    Type: Application
    Filed: February 9, 2022
    Publication date: May 26, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11342297
    Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen, Sen-Bor Jan, Sung-Feng Yeh
  • Patent number: 11335656
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Publication number: 20220139882
    Abstract: A package structure includes a first die, a die stack structure bonded to the first die, a support structure and an insulation structure. The support structure is disposed on the die stack structure, and a sidewall of the support structure is laterally shifted from a sidewall of the die stack structure. The insulation structure is disposed on the first die and laterally wraps around the die stack structure and the support structure.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20220139885
    Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Inventors: Chih-Chia Hu, Ming-Fa Chen