Patents by Inventor Ming-Fa Chen

Ming-Fa Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021576
    Abstract: A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.
    Type: Application
    Filed: August 6, 2023
    Publication date: January 18, 2024
    Inventors: Ming-Fa Chen, Chuan-An Cheng, Sung-Feng Yeh, Chih-Chia Hu
  • Publication number: 20240021584
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Application
    Filed: August 1, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20240021597
    Abstract: A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 18, 2024
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20240021544
    Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 18, 2024
    Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
  • Publication number: 20240021583
    Abstract: Packages and methods of fabricating the same are provided. The package includes a first die, wherein the first die includes a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20240014181
    Abstract: A semiconductor structure includes a first die and a plurality of first dummy pads. The first die includes a first interconnect structure and a first active pad electrically connected to the first interconnect structure. The first dummy pads laterally surround the first active pad and are electrically floating.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Ching-Jung Yang
  • Publication number: 20240014095
    Abstract: A semiconductor package including a thermally conductive bridge and a method of forming are provided. The semiconductor package may include a first semiconductor device having a first substrate and first contact pads on the first substrate, a first thermally conductive feature on the first substrate and extending into the first substrate, a second semiconductor device over the first substrate, wherein the second semiconductor device may include second contact pads electrically connected to the first contact pads, a first thermally conductive bridge over the first semiconductor device and beside the second semiconductor device, and a first encapsulant over the first semiconductor device and along sidewalls of the second semiconductor device and the first thermally conductive bridge.
    Type: Application
    Filed: July 7, 2022
    Publication date: January 11, 2024
    Inventor: Ming-Fa Chen
  • Publication number: 20240014103
    Abstract: Provided is a package structure including a bottom die, a top die, an insulating layer, a circuit substrate, a dam structure, and an underfill. The top die is bonded on a front side of the bottom die. The insulating layer is disposed on the front side of the bottom die to laterally encapsulate a sidewall of the top die. The circuit substrate is bonded on a back side of the bottom die through a plurality of connectors. The dam structure is disposed between the circuit substrate and the back side of the bottom die, and connected to the back side of the bottom die. The underfill laterally encapsulates the connectors and the dam structure. The dam structure is electrically isolated from the circuit substrate by the underfill. A method of forming the package structure is also provided.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
  • Publication number: 20240014199
    Abstract: A semiconductor package includes a first die including an optical coupler, a second die disposed on the first die, and a transparent encapsulation material disposed on the first die. The second die includes a substrate and a transparent portion disposed within the substrate and optically coupled to the optical coupler. The transparent encapsulation material extends along sidewalls of the substrate of the second die.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11869819
    Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzuan-Horng Liu, Chao-Hsiang Yang, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11862599
    Abstract: A method includes placing a first package component. The first package component includes a first alignment mark and a first dummy alignment mark. A second package component is aligned to the first package component. The second package component includes a second alignment mark and a second dummy alignment mark. The aligning is performed using the first alignment mark for positioning the first package component, and using the second alignment mark for position the second package component. The second package component is bonded to the first package component to form a package, with the first alignment mark being bonded to the second dummy alignment mark.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Ming-Fa Chen
  • Patent number: 11862605
    Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Chen-Hua Yu
  • Patent number: 11862590
    Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
  • Patent number: 11856800
    Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Wen-Chih Chiou, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 11855063
    Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 11854921
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Tzuan-Horng Liu
  • Patent number: 11854990
    Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Pin Hu, Chen-Hua Yu, Ming-Fa Chen, Jing-Cheng Lin, Jiun Ren Lai, Yung-Chi Lin
  • Patent number: 11854967
    Abstract: Semiconductor packages are provided. One of the semiconductor packages includes an integrated circuit, a die, an encapsulant and an inductor. The die is bonded to the integrated circuit. The encapsulant encapsulates the die over the integrated circuit. The inductor includes a plurality of first conductive patterns and a plurality of second conductive patterns. The first conductive patterns penetrate through the encapsulant. The second conductive patterns are disposed over opposite surfaces of the encapsulant. The first conductive patterns and the second conductive patterns are electrically connected to one another to form a spiral structure having two ends.
    Type: Grant
    Filed: May 17, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11854918
    Abstract: A semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 11855042
    Abstract: A method of manufacturing a semiconductor structure includes following operations. A substrate is provided. A first die is disposed over the substrate. A second die is provided. The second die includes a via extended within the second die. The second die is disposed over the substrate. A molding is formed around the first die and second die. An interconnect structure is formed. The interconnect structure includes a dielectric layer and a conductive member. The dielectric layer is disposed over the molding, the first die and the second die. The conductive member is surrounded by the dielectric layer. The via is formed by removing a portion of the second die to form a recess extended within the second die and disposing a conductive material into the recess.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Wen-Chih Chiou, Sung-Feng Yeh