Abstract: A memory device includes a substrate, a first digit line, a first capacitor and a metal shield. The substrate has a plurality of active areas and an isolation area. The first digit line and the first capacitor are connected to a first active area of the active areas. The second digit line is connected to a second active area of the active areas. The metal shield is located on the insolation area and between the first digit line and the second digit line. The metal shield is electrically insulated with the first digit line and the second digit line.

Abstract: Systems and methods for determining mechanical properties of formation rock using, for example, millimeter-scale test samples of the formation rock are disclosed. The test samples may be single edge notched beam (SENB) test samples. The systems and methods may include performing laboratory testing on the SENB test samples and recording laboratory testing data obtained from the laboratory testing and performing a simulation on a numerical model of the SENB test samples and recording the simulation data obtained from the simulation. The laboratory testing data and the simulation data may be compared, and a determination may be made as to whether a selected degree of correlation is present between the laboratory testing data and the simulation exists. Mechanical properties of the formation rock are obtained from the simulation data when the selected degree of correlation exists between the laboratory testing data and the simulation data.

Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.

Abstract: A security method for monitoring an optical module and a three-dimensional sensor using the same apply electromagnetic induction to the three-dimensional sensor to monitor the optical module and a light source module. Two inductive coils corresponding to each other are arranged on the light source module and the optical module. An alternative current is inputted to one of the inductive coils and another of the inductive coils generates an inductive current. The value of the inductive current is continuously detected. When the value of the inductive current varies, the abnormality of the optical module is determined to shut down the light source module, thereby completing the security mechanism of the three-dimensional sensor.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: A regeneration method for a liquefied gas thiol-removing alkaline solution comprising the following steps: performing an oxygenation reaction with respect to a liquefied gas thiol-removing alkaline solution and, at the same time, utilizing a high air-liquid condition to extract a disulfide and a polysulfide into a gas phase, thus completing the separation of the disulfide and the polysulfide from the alkaline solution, and implementing the regeneration of the liquefied gas thiol-removing alkaline solution.

Abstract: A security method for monitoring an optical module and a three-dimensional sensor using the same apply electromagnetic induction to the three-dimensional sensor to monitor the optical module and a light source module. Two inductive coils corresponding to each other are arranged on the light source module and the optical module. An alternative current is inputted to one of the inductive coils and another of the inductive coils generates an inductive current. The value of the inductive current is continuously detected. When the value of the inductive current varies, the abnormality of the optical module is determined to shut down the light source module, thereby completing the security mechanism of the three-dimensional sensor.

Abstract: A butterfly valve includes a valve body, a stem, a disc, and a stopper. The valve body has a first through hole, a second through hole and a flange. An axial central line of the second through hole and an axial central line of the first through hole are perpendicular to each other. The flange radially extends from a surface surrounding the first through hole and extends into an inner side of the first through hole. The stem is accommodated inside the second through hole and extends into the first through hole. The disc is formed on a surface thereof with a first engaging portion while the stopper is formed with a second engaging portion. The first engaging portion and the second engaging portion are respectively embedded with a first part and a second part of the stem. The stopper is rotated by the stem and abuts against the flange when the disc closes an open end of the first through hole and continues to rotate.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.

Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.

Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.

Abstract: An apparatus comprises a memory slot mounted to a main board, an expansion slot mounted to the main board and electrically coupled to the memory slot, a backup power module receivable in the expansion slot, and a main power source electrically coupled to the expansion slot and the memory slot. During normal operation, the main power source supplies electrical power to the memory slot and charge the backup power module. In the event of power loss or main power source failure, the backup power module discharges electrical power to the memory slot.

Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.

Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.

Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.

Abstract: A functionless transistor device includes a semiconductor substrate, a channel, a first source/drain, a second source/drain, a gate and a gate dielectric layer. The channel includes a first channel extending in a lateral direction, and a second channel extending in a vertical direction. The first source/drain is in contact with the first channel. The second source/drain is in contact with the second channel. The channel, the first source/drain and the second source/drain have the same doping type. The gate is disposed over an upper surface of the first channel and side surfaces of the second channel, and the gate has a second doping type opposite to the first doping type. The gate dielectric layer is disposed between the gate and the channel.

Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.