Patents by Inventor Ming Fan

Ming Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971517
    Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 6, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yi Hua Liu, Jun Liu, Lu Ming Fan
  • Patent number: 10877080
    Abstract: A security method for monitoring an optical module and a three-dimensional sensor using the same apply electromagnetic induction to the three-dimensional sensor to monitor the optical module and a light source module. Two inductive coils corresponding to each other are arranged on the light source module and the optical module. An alternative current is inputted to one of the inductive coils and another of the inductive coils generates an inductive current. The value of the inductive current is continuously detected. When the value of the inductive current varies, the abnormality of the optical module is determined to shut down the light source module, thereby completing the security mechanism of the three-dimensional sensor.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: December 29, 2020
    Assignees: Interface Technology (Chengdu) Co., Ltd., Interface Optoelectronics (Shenzhen) Co., Ltd., General Interface Solutions Limited
    Inventors: Chia-Ming Fan, Ying Long Ye
  • Publication number: 20200321215
    Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 8, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Ming FAN, Zi Qun HUA, Bi Feng LI, Qingchen CAO, Yaobin FENG, Zhiliang XIA, Zongliang HUO
  • Publication number: 20200291320
    Abstract: A regeneration method for a liquefied gas thiol-removing alkaline solution comprising the following steps: performing an oxygenation reaction with respect to a liquefied gas thiol-removing alkaline solution and, at the same time, utilizing a high air-liquid condition to extract a disulfide and a polysulfide into a gas phase, thus completing the separation of the disulfide and the polysulfide from the alkaline solution, and implementing the regeneration of the liquefied gas thiol-removing alkaline solution.
    Type: Application
    Filed: April 12, 2019
    Publication date: September 17, 2020
    Inventors: Xuesheng Hu, Fei Gao, Shengbao He, Yingwen Li, Xiao Li, Ming Fan, Weigang Dong, Jing Chen, Wei Li, Qing Hu, Yuan Wang, Huaqun Zhou
  • Publication number: 20200256906
    Abstract: A security method for monitoring an optical module and a three-dimensional sensor using the same apply electromagnetic induction to the three-dimensional sensor to monitor the optical module and a light source module. Two inductive coils corresponding to each other are arranged on the light source module and the optical module. An alternative current is inputted to one of the inductive coils and another of the inductive coils generates an inductive current. The value of the inductive current is continuously detected. When the value of the inductive current varies, the abnormality of the optical module is determined to shut down the light source module, thereby completing the security mechanism of the three-dimensional sensor.
    Type: Application
    Filed: March 13, 2019
    Publication date: August 13, 2020
    Inventors: CHIA-MING FAN, YING LONG YE
  • Publication number: 20200240538
    Abstract: A butterfly valve includes a valve body, a stem, a disc, and a stopper. The valve body has a first through hole, a second through hole and a flange. An axial central line of the second through hole and an axial central line of the first through hole are perpendicular to each other. The flange radially extends from a surface surrounding the first through hole and extends into an inner side of the first through hole. The stem is accommodated inside the second through hole and extends into the first through hole. The disc is formed on a surface thereof with a first engaging portion while the stopper is formed with a second engaging portion. The first engaging portion and the second engaging portion are respectively embedded with a first part and a second part of the stem. The stopper is rotated by the stem and abuts against the flange when the disc closes an open end of the first through hole and continues to rotate.
    Type: Application
    Filed: June 27, 2019
    Publication date: July 30, 2020
    Inventor: Yi-Ming FAN
  • Patent number: 10727056
    Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Ming Fan, Zi Qun Hua, Bi Feng Li, Qingchen Cao, Yaobin Feng, Zhiliang Xia, Zongliang Huo
  • Publication number: 20200235121
    Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 23, 2020
    Inventors: Yi Hua Liu, Jun Liu, Lu Ming Fan
  • Publication number: 20200161756
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10627442
    Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 21, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Shih-Ting Lin, Kung-Ming Fan, Hung-Hsiang Xsiao
  • Patent number: 10587041
    Abstract: An electronic package structure is provided, including a substrate with an electronic component, an antenna element and a shielding element disposed on the substrate. The shielding element is positioned between the antenna element and the electronic component to prevent electromagnetic interference (EMI) from occurring between the antenna element and the electronic component. A method for fabricating the electronic package structure is also provided.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 10, 2020
    Assignee: Silicon Precision Industries Co., Ltd.
    Inventors: Chih-Yuan Shih, Chih-Hsien Chiu, Yueh-Chiung Chang, Tsung-Li Lin, Chi-Pin Tsai, Chien-Cheng Lin, Tsung-Hsien Tsai, Heng-Cheng Chu, Ming-Fan Tsai
  • Patent number: 10580510
    Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kung-Ming Fan
  • Publication number: 20200064895
    Abstract: An apparatus comprises a memory slot mounted to a main board, an expansion slot mounted to the main board and electrically coupled to the memory slot, a backup power module receivable in the expansion slot, and a main power source electrically coupled to the expansion slot and the memory slot. During normal operation, the main power source supplies electrical power to the memory slot and charge the backup power module. In the event of power loss or main power source failure, the backup power module discharges electrical power to the memory slot.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 27, 2020
    Inventors: SHIH MING FAN CHIANG, ZHI DA HUANG, CHANG-HSING LEE, CHIHWEI WU
  • Publication number: 20190214352
    Abstract: The disclosure provides an electronic package, including a carrier, an electronic component disposed on the carrier, a buffer, and an antenna structure, wherein the antenna structure includes a metal frame disposed on the carrier and a wire disposed on the carrier and electrically connected to the metal frame, and the buffer covers the wire so as to reduce the emission wave speed of the wire and thus the wavelength is shorten, thereby satisfying the length requirement of the antenna within the limited space of the carrier and achieving an operating frequency radiated as required.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 11, 2019
    Inventors: Ming-Fan Tsai, Chih-Hsien Chiu, Tsung-Hsien Tsai, Chao-Ya Yang, Chia-Yang Chen
  • Publication number: 20190198128
    Abstract: The present disclosure provides a test system, and a method of operating the same. The test system is for testing a DRAM (dynamic random access memory). The DRAM includes an array including a first memory row and a second memory row. The first memory row includes a first word line. The second memory row includes a second word line and a test cell. The second word line is immediately adjacent to the first word line. The test cell is controllable by the second word line. The test system includes a work station. The work station is configured to evaluate a row hammer effect on the second memory row based on a leakage charge, caused by an AC component of a pulse applied to the first word line, from the test cell.
    Type: Application
    Filed: January 8, 2018
    Publication date: June 27, 2019
    Inventor: KUNG-MING FAN
  • Publication number: 20190178931
    Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.
    Type: Application
    Filed: March 5, 2018
    Publication date: June 13, 2019
    Inventors: Shih-Ting LIN, Kung-Ming FAN, Hung-Hsiang XSIAO
  • Publication number: 20190172920
    Abstract: A functionless transistor device includes a semiconductor substrate, a channel, a first source/drain, a second source/drain, a gate and a gate dielectric layer. The channel includes a first channel extending in a lateral direction, and a second channel extending in a vertical direction. The first source/drain is in contact with the first channel. The second source/drain is in contact with the second channel. The channel, the first source/drain and the second source/drain have the same doping type. The gate is disposed over an upper surface of the first channel and side surfaces of the second channel, and the gate has a second doping type opposite to the first doping type. The gate dielectric layer is disposed between the gate and the channel.
    Type: Application
    Filed: January 4, 2018
    Publication date: June 6, 2019
    Inventors: Tsung-Yu TSAI, Ching-Chia HUANG, Kung-Ming FAN
  • Publication number: 20190157082
    Abstract: A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 23, 2019
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lu Ming FAN, Zi Qun HUA, Bi Feng LI, Qingchen CAO, Yaobin FENG, Zhiliang XIA, Zongliang HUO
  • Patent number: 10208732
    Abstract: The present invention relates to an intelligent wind turbine generator, which comprises a first blade module, a second blade module, a power generating module, and a control module. The second blade module is disposed at the first blade module. The power generating module is connected with the first and second blade modules. The control module is connected with the power generating module, the first blade module, and the second blade module. The first and second blade modules rotate, driving the power generating module to generate power. The control module detects a voltage value generated by the power generating module and judges if the voltage value is greater or lower than a predetermined value. The control module controls whether the first and second blade modules overlap or not. The intelligent wind turbine generator is able to switch automatically the blade number of the wind turbine generator.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: February 19, 2019
    Assignee: Chung Yuan Christian University
    Inventors: Huei-Chu Weng, Chen-Ming Fan, Hung-Yu Chen, Kevin Buana
  • Patent number: 10199317
    Abstract: An electronic package includes a circuit structure having a first metal layer, a packaging layer formed on the circuit structure, and a second metal layer formed on the packaging layer and separated from the first metal layer at a distance. The first metal layer and the second metal layer constitute an antenna structure. Since the second metal layer is formed on a portion of a surface of the packaging layer, a propagating wave emitted by the first metal layer cannot pass through the second metal layer, but a surface of the packaging layer not covered by the second metal layer. Therefore, the propagating wave can be transmitted to a predetermined target, and the electronic package performs the function of an antenna.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chih-Hsien Chiu, Chia-Yang Chen, Ying-Wei Lu, Jyun-Yuan Jhang, Ming-Fan Tsai