Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A method for fabricating a portion of an integrated circuit on a semiconductor substrate. The method includes cleaning the surface of the substrate, and forming a thin insulate over the substrate. The method also includes depositing a high dielectric constant (high-k) material over the thin insulate, and then performing a hydrogen-based anneal on the high-k material. The method further includes performing an oxygen-based anneal on the high-k material, wherein the hydrogen-based and oxygen-based anneals occur sequentially.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: The invention structure of wheel rim cover includes: one cover body whose disc surface forming many costal bodies and engraved holes; many fasteners are set on the same outer hole edge of the near end hole of the engraved hole; such fasteners become a group, surrounding outside of the end hole of the same engraved hole, and are jointly supported by a coil spring. The whole cover body can make use of the fasteners to latch on the end hole of the engraved hole of the targeted wheel rim and be fastened on the wheel rim.

Abstract: A method of making a semiconductor device having a silicon dioxide based gate with improved dielectric properties including providing a silicon based substrate having active areas defined therein. Thermally growing a silicon dioxide based gate from the silicon based substrate. Nitriding the silicon dioxide based gate to provide a nitrided silicon dioxide based gate and to increase the dielectric constant of the silicon dioxide based gate without substantially increasing thickness of the silicon dioxide based gate.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: An extensional hubcap docking structure. The structure includes anchoring mounts positioned on the back surface of a hubcap. Clip components are coupled onto the anchoring mounts, and elastic components are situated between each hubcap anchoring mount and clip component. When the hubcap is fully installed onto the wheel of a tire and the hubcap is subjected to an outward force that subsequently pulls the anchoring mounts, the elastic components compress and rebound such that the hubcap is kept safely and tightly positioned on the wheel rim.

Abstract: An extensional hubcap docking structure comprised of anchoring mounts disposed on the back surface of a hubcap and clip components coupled onto the anchoring mounts. Elastic components are situated between the hubcap anchoring mounts and the clip components. When the hubcap is fully installed onto the tire wheel and the hubcap is subjected to an outward force that displaces the anchoring mounts outward, the elastic components deform and shift such that the hubcap is kept safely and tightly positioned on the wheel rim.

Abstract: A rotating hubcap comprised of a hubcap having a hole in the center, a seat, and a bearing installed in the seat. A turntable is pivotably positioned in the seated bearing, a revolving member is fastened onto the turntable, the opening in the center of the revolving member is sleeved onto the shaft member on the turntable, and the shaft members on the turntable exposed through the revolving member opening are then inserted into the bearing, such that the revolving member gyrates independently as a motor vehicle is driven.

Abstract: A method for fabricating a portion of an integrated circuit on a semiconductor substrate. The method includes cleaning the surface of the substrate, and forming a thin insulate over the substrate. The method also includes depositing a high dielectric constant (high-k) material over the thin insulate, and then performing a hydrogen-based anneal on the high-k material. The method further includes performing an oxygen-based anneal on the high-k material, wherein the hydrogen-based and oxygen-based anneals occur sequentially.

Abstract: At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.

Abstract: A method for forming an improved gate stack structure having improved electrical properties in a gate structure forming process A method for forming a high dielectric constant gate structure including providing a silicon substrate comprising exposed surface portions; forming an interfacial layer over the exposed surface portions having a thickness of less than about 10 Angstroms; forming a high dielectric constant metal oxide layer over the interfacial layer having a dielectric constant of greater than about 10; forming a barrier layer over the high dielectric constant metal oxide layer; forming an electrode layer over the barrier layer; and, etching according to an etching pattern through a thickness of the electrode layer, barrier layer, high dielectric constant material layer, and the interfacial layer to form a high dielectric constant gate structure.

Abstract: The present invention makes use of an opening of a latch cover opening to engage the first loose leaf with the second loose leaf at a pivotal opening with a diameter smaller than the opening of the latch cover of the first loose leaf, and the latch cover of the first loose leaf is located between the two axle covers of the second loose leaf after they are coupled. Therefore, the two will not be separated from each other in the front-rear direction easily, so that the first and second loose leaves can be removed and assembled, and fixed securely after the assembling.

Abstract: An extensional hubcap docking structure. The structure includes anchoring mounts positioned on the back surface of a hubcap. Clip components are coupled onto the anchoring mounts, and elastic components are situated between each hubcap anchoring mount and clip component. When the hubcap is fully installed onto the wheel of a tire and the hubcap is subjected to an outward force that subsequently pulls the anchoring mounts, the elastic components compress and rebound such that the hubcap is kept safely and tightly positioned on the wheel rim.

Abstract: Novel methods for improving the within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate. According to a first embodiment, a gate oxide layer is formed on a wafer using conventional oxidation parameters and equipment. Next, the edge-thick gate oxide layer is nitridated using a center-thick plasma nitridation profile to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer. According to a second embodiment, the wafer substrate is first nitridated and then oxidized to form the gate oxide layer. The nitrogen incorporated into the wafer surface during the nitridation step retards oxidation of the wafer at the wafer edge to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer.

Abstract: In the present invention, an edge is extended from the rim of a circular disc of a wheel cover, and such edge is the portion that the circular disc of the wheel cover exceeds the rim of the steel wheel, having an appropriated width to sufficiently block the thickness of the tire and make the tire look thinner.

Abstract: The present invention comprises a footrest with a poking rod; a bumper with an embedding hole is formed on the footrest; a latch member having two bent latch plates, each latch plate having a latch groove with a corresponding concave neck disposed inwardly, and a corresponding concave latch fork inwardly disposed, a latch wing outwardly disposed is formed on the latch groove; a corresponding outwardly protruded extension section is defined under the latch groove; such that the poking rod is clipped by the two plates of the latch member, and engaged by the latch fork. The footrest with the latch member and the poking rod are fully embedded and inserted into the embedding hole on the base of the bumper and secured into a fixed position.