Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

Abstract: Provided are novel vaccines for prophylactic treatment of SARS-CoV-2 infections and COVID-19 and methods of making the vaccines.

Abstract: A gated tri-state (G3S) inverter includes: first, second and third transistors of a first dopant type (D1 transistors) and first, second and third transistors of a second dopant type (D2 transistors) serially connected between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type; gate terminals of an alpha one of the noted D1 transistors and an alpha one of the noted D2 transistors being configured to receive an input signal; gate terminals of a beta one of the noted D1 transistors and a beta one of the noted D2 transistors being configured to receive a gating signal; a gate terminal of a gamma one of the noted D2 transistors being configured to receive an enable signal; and a gate terminal of a gamma one of the noted D1 transistors being configured to receive an enable_bar signal.

Abstract: An wafer probe device is provided, including a holder, and a probe card. The holder has a holding surface for holding a wafer. The probe card has a probing side for probing the wafer. Wherein the holder and the probe card are disposed on the ground, and the holding surface of the holder and the probing side of the probe card are perpendicular to the ground. Wherein when the holder holds the wafer to move upwardly toward the probe card into a probing position, the probed surface of the wafer is in contact with the probe card, and the probe surface is perpendicular to the ground.

Abstract: A rapid detection device for multi-channel sporadic transient partial discharge, comprising a CPU and several partial discharge detection circuits. The partial discharge detection circuits are connected to a plurality of ports of the CPU one to one, respectively. First, a partial discharge pulse signal is filtered and amplified by means of a partial discharge pulse signal processing module in the partial discharge detection circuits, and is then inputted to a comparator, and a reference voltage passes through the CPU and is sent to a reference voltage processing module for amplification, filtering and other processing, and then is inputted to the comparator, so that the comparator processes same according to the partial discharge pulse signal and the reference voltage and then inputs same to a trigger. Finally, according to a level signal at an output terminal of the trigger, the CPU determines whether partial discharge occurs in a circuit to be detected.

Abstract: A golf club head includes a club head main body, a club head complementary component, and a protection component. The club head main body defines an opening which includes an inner opening section and an outer opening section spatially connected to and located outside the inner opening section. The club head complementary component is disposed in the inner opening section and connected to the club head main body. The protection component is disposed in the outer opening section and connected to the club head complementary component to cover the club head complementary component. The protection component is made of a carbon fiber impregnated with thermoplastic polyurethane, and has a Shore D hardness ranging from 40 to 70.

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

Abstract: An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.

Abstract: Embodiments for operational envelope detection (OED) with situational assessment are disclosed. In some embodiments, a method comprises: determining at least one current or future constraint for a trajectory of a vehicle in an environment that is associated with the vehicle becoming immobile for an extended period of time; determining a stopping-reason for immobility of the vehicle based on determining the at least one current or future constraint for the trajectory of the vehicle in the environment; identifying a timeout threshold based on the stopping-reason, wherein the timeout threshold is an amount of time a planning system of the vehicle will wait before initiating at least one remedial action to address the immobility; identifying that the timeout threshold is satisfied; and initiating the at least one remedial action for the vehicle based on the identifying that the timeout threshold is satisfied.

Abstract: A phase interpolating (PI) system includes: a PI stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component. The capacitive component is tunable to exhibit non-zero capacitances. The capacitive component has a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

Abstract: Embodiments for operational envelope detection (OED) with situational assessment are disclosed. Embodiments herein relate to an operational envelope detector that is configured to receive, as inputs, information related to sensors of the system and information related to operational design domain (ODD) requirements. The OED then compares the information related to sensors of the system to the information related to the ODD requirements, and identifies whether the system is operating within its ODD or whether a remedial action is appropriate to adjust the ODD requirements based on the current sensor information. Other embodiments are described and/or claimed.

Abstract: A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.

Abstract: The disclosure provides a voltage droop monitor (VDM) and a voltage droop monitoring method. The method includes: receiving a first reference clock signal and delaying the first reference clock signal as a first clock signal; delaying the first clock signal as a corresponding second clock signal; receiving the corresponding second clock signal from the corresponding first DCDL and generating a corresponding third clock signal via modifying a phase of the corresponding second clock signal; receiving the corresponding third clock signal; receiving a second reference clock signal; and collectively outputting a TDC code combination based on the second reference clock signal and the corresponding third clock signal, wherein the TDC code combination varies in response to a voltage variation of a to-be-monitored voltage.

Abstract: A semiconductor device includes a first doped zone and a second doped zone in a first semiconductor material, the first doped zone being separated from the second doped zone; an isolation structure between the first doped zone and the second doped zone; and a first line segment over a top surface of the first doped zone, where the ends of the first line segment and the ends of the second line are over the isolation structure. The first line segment and the second line segment have a first width; and a dielectric material is between the first line segment and the second line segment and over the isolation structure. The first width is substantially similar to a width of a gate electrode in the semiconductor device.

Abstract: A device includes a substrate having a first surface and a second surface opposite to the first surface; a thin-film transistor array disposed on the first surface, including a plurality of transistors; a plurality of diodes disposed on the thin-film transistor array; a plurality of conductive structures penetrating through the substrate from the first surface to the second surface, wherein the plurality of conductive structures are corresponding to the plurality of diodes and electrically connected to the plurality of diodes; a driver unit disposed on the second surface of the substrate; a patterned conductive layer disposed between the substrate and the driver unit; a protection layer disposed on the patterned conductive layer, wherein the protection layer has an opening that exposes the patterned conductive layer; and a conductive material disposed in the opening.

Abstract: A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

Abstract: A key structure is provided. The key structure includes a base plate, a keycap, a positioning element and a rod. The base plate has a through hole. The positioning element is engaged with the through hole. A projection area of the positioning element on the base plate along a lifting direction of the keycap is larger than an area of the through hole.

Abstract: Methods and devices are provided herein for enhancing robustness of a bipolar electrostatic discharge (ESD) device. The robustness of a bipolar ESD device includes providing an emitter region and a collector region adjacent to the emitter region. An isolation structure is provided between the emitter region and the collector region. A ballasting characteristic at the isolation structure is modified by inserting at least one partition structure therein. Each partition structure extends substantially abreast at least one of the emitter and the collector regions.

Abstract: A wafer probe device is provided, including a holder and a probe card. The holder is configured to hold a wafer. The probe card is disposed on the ground, between the holder and the ground, and under the holder. The probing side of the probe card faces away from the ground. The holder moves the wafer toward the probe card, and a probed surface of the wafer contacts the probe card.