Patents by Inventor Ming Han

Ming Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250044157
    Abstract: An electronic device includes an outer case, a circuit substrate, a thermopile sensor chip, a filter structure, and a waterproof structure. The outer case has an opening. The circuit substrate is disposed inside the outer case. The thermopile sensor chip is disposed on the circuit substrate. The filter structure is disposed above the thermopile sensor chip. The waterproof structure is surroundingly connected between the filter structure and the outer case, wherein the waterproof structure has a through hole for exposing the filter structure and communicated with the opening of the outer case.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: MING-HAN TSAI, CHIH-MING SUN, JIAN-CHENG LIAO
  • Publication number: 20250045736
    Abstract: Certain aspects of the present disclosure provide techniques for securely accessing a wallet on a blockchain. An example method generally includes receiving a request to access a wallet on a blockchain. The request generally includes an authorization code associated with the wallet and user credentials associated with an owner of the wallet. A first portion of a private key is decrypted based on the authorization code and a salt associated with the user credentials, and a second portion of the private key is decrypted based on credentials associated with an application through which the wallet is accessed. Access to the wallet is granted based on the decrypted first portion and the decrypted second portion of the private key.
    Type: Application
    Filed: August 1, 2024
    Publication date: February 6, 2025
    Inventors: Ming Chang DONG, Huaiting HUANG, Ming Chang SHIH, Zhiyu ZHANG, Chi Huang FAN, Jordan FORSSMAN, Jayaprakash PAKALAPATI, Ka Wai TSUI, Gagneet Singh MAC, Yi-An LIN, Li TAO, Chiang HAN-ZHEN, Tzuyu HSU, Liu Chien WEI, Debra PENG, Nikhil KUMAR, Kok Peng LIM, Andrew ZIMMER, Justin BELL, Yingying ZHENG
  • Publication number: 20250048611
    Abstract: A method of forming a semiconductor structure includes forming a fin over a semiconductor substrate, forming an isolation region on sidewalls of the fin, forming a metal gate over the fin and the isolation region, etching the metal gate to form a trench through the isolation region, passivating the top portion of the semiconductor substrate exposed in the trench to form a dielectric layer at a bottom of the trench, and depositing a dielectric material in the trench to form a dielectric structure. The dielectric structure divides the metal gate into two sections.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Yen Yu Chen, Ming-Yen Tsai, Wen-Hsing Hsieh, Ying-Han Chiou
  • Patent number: 12219538
    Abstract: This application provides an information indication method and an apparatus. In this application, a sending apparatus generates and sends a first frame, the first frame includes at least one piece of sub-time resource indication information, and each piece of sub-time resource indication information is in a one-to-one correspondence with one of at least one response apparatus. In addition, each piece of sub-time resource indication information includes a time resource at which the corresponding response apparatus sends feedback information for the first frame to the sending apparatus and a time resource at which the sending apparatus sends acknowledgment information for the feedback information to the corresponding response apparatus, so that the at least one response apparatus and the sending apparatus that sends the first frame can simultaneously perform beamforming training, thereby improving effectiveness of beamforming training performed on the sending apparatus and the at least one response apparatus.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: February 4, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiao Han, Mengyao Ma, Yan Xin, Chenlong Jia, Ming Gan
  • Patent number: 12218060
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Meng-Pei Lu, Chin-Lung Chung, Ming-Han Lee, Shau-Lin Shue
  • Publication number: 20250040214
    Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chiung-Yu Cho, Po-Yuan Tseng, Min-Chiao Lin, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang
  • Patent number: 12211915
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Patent number: 12211788
    Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 12211740
    Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wei Li, Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 12211799
    Abstract: Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Han Lee, Shin-Yi Yang, Shau-Lin Shue
  • Publication number: 20250029550
    Abstract: A display panel and a pixel circuit thereof are provided. A pulse width signal generator turns on a charge sharing switch during a light-emitting period, and performs charge sharing with a control end of a positive feedback switch of a positive feedback circuit, so as to control the positive feedback switch to provide a positive feedback voltage to the pulse width signal generator to increase a voltage at an output end of the pulse width signal generator and thus to accelerate a rising speed of a voltage for controlling a driving current generator to provide a driving current.
    Type: Application
    Filed: July 16, 2024
    Publication date: January 23, 2025
    Applicant: AUO Corporation
    Inventors: Chih-Lung Lin, Yi-Jui Chen, Cheng-Han Ke, Ming-Yang Deng, Chia-Tien Peng
  • Publication number: 20250030233
    Abstract: Provided are calibrating method and system of setting value of grid-related relay protection of new energy station, wherein generating module of calibrating template generates setting value calibrating template of target new energy station based on names of each of protective setting value items and units of each of protective setting value items of target new energy station; generating module of setting value table to be calibrated generates setting value table to be calibrated of target new energy station based on actual values of each of protective setting value items and setting value calibrating template; determining module of standard setting value table determines standard setting value table of target new energy station from protective setting value calibration database according to new energy station number of target new energy station; and calibrating module of protective setting value calibrates setting value table to be calibrated according to standard setting value table.
    Type: Application
    Filed: March 7, 2024
    Publication date: January 23, 2025
    Applicant: INNER MONGOLIA POWER (GROUP) CO., LTD INNER MONGOLIA POWER RESEARCH INSTITUTE
    Inventors: Chen GAO, Minfu A, Zaixin YANG, Lixin XING, Ming ZHONG, Tao HAN, Rulei HAN, Sitai YA, Wei ZHANG, Guangfei LV
  • Publication number: 20250026977
    Abstract: This disclosure relates to thermal stimuli-responsive surfactant mixtures useful for reducing water/oil interfacial tension at high temperatures and increasing water/oil interfacial tension at low temperatures. The disclosure also relates to methods of using the surfactant mixtures for enhanced oil recovery applications.
    Type: Application
    Filed: October 9, 2024
    Publication date: January 23, 2025
    Inventors: Limin Xu, Ming Han, Tianping Huang
  • Patent number: 12205886
    Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
  • Publication number: 20250022914
    Abstract: A method of forming a nanosheet FET is provided. A plurality of first and second semiconductor layers are alternately formed on a substrate. The first and second semiconductor layers are patterned into a plurality of stacks of semiconductor layers separate from each other by a space along a direction. Each stack of semiconductor layers has a cross-sectional view along the direction gradually widening towards the substrate. An epitaxial feature is formed in each of the spaces. The patterned second semiconductor layers are then removed from each of the stacks of semiconductor layers.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chiung-Yu CHO, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG
  • Publication number: 20250019586
    Abstract: A system and a method for making and using an enhanced oil recovery (EOR) fluid. The EOR fluid includes a base fluid, an anionic-nonionic surfactant including one of sodium alkylphenol ethoxylate carboxylate (APEC), sodium alkyl ethoxylate carboxylate (AEC), sodium alkylphenol ethoxylate sulfate (APES), or sodium alkyl ethoxylate sulfate (AES), and a second surfactant including a cationic surfactant including an alkyl pyridine salt.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Inventors: Limin Xu, Ming Han, Tianping Huang
  • Publication number: 20250011640
    Abstract: A method for reducing the interfacial tension between a hydrocarbon fluid and a surfactant mixture solution during chemical enhanced oil recovery includes introducing a surfactant mixture solution to a hydrocarbon-bearing reservoir, thereby reducing the interfacial tension at a liquid-liquid interface of the hydrocarbon fluid and the surfactant mixture solution. The surfactant mixture solution includes a polyacrylamide polymer, a brine solution, and a surfactant mixture. The surfactant mixture includes an anionic surfactant, a cationic surfactant, and a nonionic surfactant. The anionic surfactant may include organosulfate. The cationic surfactant may include a quaternary ammonium, a brominated trimethylammonium, a chloride trimethylammonium, or combinations thereof. The nonionic surfactant may include a polyoxyethylene fatty acid ester, a phenylated ethoxylate, or combinations thereof.
    Type: Application
    Filed: June 25, 2024
    Publication date: January 9, 2025
    Applicant: Saudi Arabian Oil Company
    Inventors: Limin Xu, Ming Han, Tianping Huang
  • Publication number: 20250003802
    Abstract: The present invention provides a far infrared (FIR) sensor device formed on a substrate, wherein the FIR sensor device includes: a sensor region, which is formed on the substrate, and is configured to operably sense a far infrared signal; and a sensor dielectric layer, which is formed on the sensor region, wherein a thickness of the sensor dielectric layer is determined by a sacrificial metal layer.
    Type: Application
    Filed: September 16, 2024
    Publication date: January 2, 2025
    Inventors: Ming-Han Tsai, Chih-Fan Hu
  • Patent number: 12181327
    Abstract: A cryogenic propellant rocket engine, a flowmeter calibration system and method for the cryogenic propellant rocket engine have been provided. The flowmeter calibration system for the cryogenic propellant rocket engine includes a container filling unit, a container, a supply pipeline, a weighing unit, a quick recovery container, a weighing and filling recovery unit and a recovery unit which are sequentially connected; the container filling unit is configured to connect a tank wagon with the container; and the supply pipeline includes a temperature sensor and a pressure sensor, as well as a first isolation valve, a reference flowmeter, a calibration flow adjusting manual valve, a vertical main pipe and N circumferentially and uniformly distributed horizontal pipes which are sequentially connected by a pipeline.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 31, 2024
    Assignee: Xi'an Aerospace Propulsion Test Technology Institute
    Inventors: Binyun Tang, Yu Chen, Ming Han, Hongpeng Xu, Li Guo, Jibin Shen, Qiang Gao, Yan Gao
  • Publication number: 20240409804
    Abstract: A scale inhibitor fluid includes 0.001 ppm to 100 ppm of a phosphonate compound, 20 ppm to 400 ppm of a cation-containing surfactant, and an aqueous fluid. The cation-containing surfactant includes at least one of a single positively charged cation-containing surfactant, a double positively charged cation-containing surfactant and a zwitterionic cation-containing surfactant. A method for inhibiting scale formation in a wellbore includes introducing a phosphonate compound, a cation-containing surfactant and an aqueous fluid to the wellbore to produce a scale inhibitor fluid.
    Type: Application
    Filed: August 20, 2024
    Publication date: December 12, 2024
    Applicant: SAUDI ARABIAN OIL COMPANY
    Inventors: Jian Hou, Ming Han, Tao Chen, Mohammed A. Bataweel, Xuan Zhang