Abstract: Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

Abstract: A semiconductor structure includes a substrate, a dielectric layer, and a graphene conductive structure. The dielectric layer is disposed on the substrate, and has an inner lateral surface that is perpendicular to the substrate. The graphene conductive structure is formed in the dielectric layer and has at least one graphene layer extending in a direction parallel to the inner lateral surface of the dielectric layer.

Abstract: Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.

Abstract: Copolymer compositions and methods of making copolymer compositions with enhanced stability in high temperature and high salinity environments. The copolymers include hydrophobic monomers and sulfonated monomers. The sulfonated monomers can include 2-acrylamido-2-methylpropane sulfonic acid and allyl sulfonate. The sulfonated monomers increase the stability of the polymers in harsh conditions, and in high temperature, high salinity environments. The sulfonated monomers also reduce or prevent the hydrolysis of acrylamide groups, and therefore enhance the stability of the copolymer. The copolymer compositions can be made with free radical polymerization and an initiation complex.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer. The semiconductor structure includes a first graphene layer disposed over the first conductive feature and a second graphene layer disposed over a portion of the second conductive feature. An etch-stop layer (ESL) is horizontally interposed between the first graphene layer and the second graphene layer. A side surface of the first or the second graphene layer directly contacts a side surface of the ESL. A third conductive feature is electrically coupled to the second conductive feature. The third conductive feature is separated from the first graphene layer by a portion of the ESL, and the third conductive feature also directly contacts a top surface of the ESL.

Abstract: There is provided an auto detection system including a thermal detection device and a host. The host controls an indication device to indicate a prompt message or detection results according to a slope variation of voltage values or 2D distribution of temperature values detected by the thermal detection device, wherein the voltage values include the detected voltage of a single pixel or the sum of detected voltages of multiple pixels of a thermal sensor.

Abstract: Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and exposed on edge surfaces of the integrated circuit die. The edge interconnect features are configured to connect with other integrated circuit dies without going through an interposer. The semiconductor device may include two or more integrated circuit dies with edge interconnect features and connected through one or more inter-chip connectors formed between the two or more integrated circuit dies. In some embodiments, the inter-chip connectors may be formed by a selective bumping process during packaging.

Abstract: A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap.

Abstract: A semiconductor device includes a substrate and an interconnect layer disposed on the substrate. The interconnect layer includes a dielectric layer and an interconnect extending through the dielectric layer. The interconnect includes a bulk metal region and a single barrier/liner layer, which serves as both a barrier layer and a liner layer and which is disposed to separate the bulk metal region from the dielectric layer.

Abstract: A composition includes an ionic liquid monomer having the following structure: where n is an integer from 1 to 5 and the ionic liquid monomer has a melting point less than 100° C. A method of making the ionic liquid includes providing a mixture comprising a sulfonic acid and a diamine in a solvent, and maintaining the mixture at a temperature ranging from 10 to 80° C. for a time ranging from 1 to 10 hours to form an ionic liquid monomer having a melting point less than 100° C. A method of making a polymer from the ionic liquid monomer is also provided.

Abstract: A cryogenic propellant rocket engine, a flowmeter calibration system and method for the cryogenic propellant rocket engine have been provided. The flowmeter calibration system for the cryogenic propellant rocket engine includes a container filling unit, a container, a supply pipeline, a weighing unit, a quick recovery container, a weighing and filling recovery unit and a recovery unit which are sequentially connected; the container filling unit is configured to connect a tank wagon with the container; and the supply pipeline includes a temperature sensor and a pressure sensor, as well as a first isolation valve, a reference flowmeter, a calibration flow adjusting manual valve, a vertical main pipe and N circumferentially and uniformly distributed horizontal pipes which are sequentially connected by a pipeline.

Abstract: The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The stack of channel structures and the gate structure are between the first and second source/drain structures. The gate structure surrounds the stack of channel structures. A first conductive wire overlies and is spaced from the semiconductor device. The first conductive wire includes a first stack of conductive layers. A first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. The first conductive contact is on a back-side of the first source/drain structure.

Abstract: A surfactant composition is provided. The composition includes chemical structure represented by Formula (1): where R1 represents a hydrocarbon group, a substituted hydrocarbon group, an alkyl ester group, or an alkyl amine having from 4 to 28 carbon atoms, and R2 and R3 represent hydrocarbon groups having from 1 to 5 carbon atoms. Also provided is a composition including a brine comprising a total salinity of at least 20,000 mg/L and the chemical structure shown in Formula (1). Methods of making a composition including the chemical structure represented by Formula (1) are also provided.

Abstract: A ferroelectric memory structure including a first conductive line, a second conductive line, and a memory cell is provided. The second conductive line is disposed on the first conductive line. The memory cell is disposed between the first and second conductive lines. The memory cell includes a switch device and a ferroelectric capacitor structure. The switch device is disposed between the first and second conductive lines. The ferroelectric capacitor structure is disposed between the first conductive line and the switch device. The ferroelectric capacitor structure includes ferroelectric capacitors electrically connected. Each of the ferroelectric capacitors includes a first conductive layer, a second conductive layer, and a ferroelectric material layer. The second conductive layer is disposed on the first conductive layer. The ferroelectric material layer is disposed between the first conductive layer and the second conductive layer.

Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.

Abstract: A scale inhibitor fluid includes 0.001 ppm to 100 ppm of a phosphonate compound, 20 ppm to 400 ppm of a cation-containing surfactant, and an aqueous fluid. The cation-containing surfactant includes at least one of a single positively charged cation-containing surfactant, a double positively charged cation-containing surfactant and a zwitterionic cation-containing surfactant. A method for inhibiting scale formation in a wellbore includes introducing a phosphonate compound, a cation-containing surfactant and an aqueous fluid to the wellbore to produce a scale inhibitor fluid.

Abstract: A plastic plural-sheet stationary includes plural plastic sheets that are superimposed on one another. The plastic plural sheets includes at least two element sheets made of plastic. The outermost element sheet includes a folding edge. Two first fusion lines are provided to securely connect the plural plastic sheets formed by the superimposed element sheets through fusion. The two first fusion lines are located on two sides of the folding edge. A spacing between the two first fusion lines is greater than twice a superimposed thickness of the plural plastic sheets. Thus, although a corrugation area is generated when the plural plastic sheets are folded along the folding line, the corrugation area is restricted between the two first fusion lines to maintain the region outside of the two first fusion lines smooth, avoiding outward spread of the corrugation area.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of intercalated graphene structures and a via. The intercalated graphene structures are disposed over the semiconductor substrate. Each of the intercalated graphene structures includes a plurality of graphene layers each extending substantially parallel to the semiconductor substrate. The via extends into at least a portion of one of the intercalated graphene structures toward the semiconductor substrate, and is in contact with edges of corresponding ones of the graphene layers of the one of the intercalated graphene structures.

Abstract: The present invention provides methods of preventing or treating coronavirus infection and reducing coronavirus infection rate in vitro with antiviral composition comprising poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS), wherein the PEDOT:PSS is selected from PEDOT:PSS aqueous solutions in various formulas. Specifically, the molar ratio of PEDOT to PSS in the PEDOT:PSS aqueous solution in the antiviral composition may be 1:1.5 to 1:6 and the resistivity of the PEDOT:PSS aqueous solution in the antiviral composition may be 100 ?/sq to 5×107 ?/sq. The antiviral composition is used to inhibit the binding between the spike protein of the coronavirus and the host cells with angiotensin-converting enzyme 2 (ACE2) on surface. The coronavirus may be SARS-CoV-2.