Abstract: A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

Abstract: An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

Abstract: A memory cell structure includes a silicon substrate, a transistor, and a capacitor. The silicon substrate has a silicon surface. The transistor is coupled to the silicon surface, the transistor includes a gate structure, a first conductive region, and a second conductive region. The capacitor has a signal electrode and a counter electrode, the capacitor is over the transistor, and the signal electrode is electrically coupled to the second conductive region of the transistor and isolated from the first conductive region of the transistor. The counter electrode includes a plurality of sub-electrodes electrically connected with each other.

Abstract: A memory structure includes a semiconductor substrate, an active region, a transistor, and a buried-WL (word line). The semiconductor substrate has an original semiconductor surface. The active region is in the semiconductor substrate and surrounded by a shallow trench isolation (STI) region. The transistor is formed based on the active region. The buried-WL (word line) extends through the active region and the STI region. The buried-WL has variable depth or width along the extension direction of the buried-WL.

Abstract: A transistor structure includes a semiconductor substrate, a gate region a spacer, a first trench, a first isolation region and a conductive region. The semiconductor substrate has an active region which has a semiconductor surface. The gate region has a first conductive portion over the semiconductor surface of the semiconductor substrate in the active region and a second conductive portion over the first conductive portion. The spacer covers a sidewall of the gate region. The first trench is formed below the semiconductor surface of the semiconductor substrate in the active region. The first isolation region is in the first trench. The conductive region is positioned on the first isolating region. Wherein a lateral length of the first conductive portion is greater than that of the second conductive portion.

Abstract: A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Abstract: A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

Abstract: A method for fabricating a MEMS sensor device. The method can include providing a substrate, forming an IC layer overlying the substrate, forming an oxide layer overlying the IC layer, forming a metal layer coupled to the IC layer through the oxide layer, forming a MEMS layer having a pair of designated sense electrode portions and a designated proof mass portion overlying the oxide layer, forming a via structure within each of the designated sense electrode portions, and etching the MEMS layer to form a pair of sense electrodes and a proof mass from the designated sense electrode portions and proof mass portions, respectively. The via structure can include a ground post and the proof mass can include a sense comb. The MEMS sensor device formed using this method can result is more well-defined edges of the proof mass structure.

Abstract: A method for a MEMS device includes receiving a diced wafer having a plurality devices disposed upon an adhesive substrate and having an associated known good device data, removing a first set of devices from the plurality of devices from the adhesive substrate in response to the known good device data, picking and placing a first set of the devices into a plurality of sockets within a testing platform, testing the first set of integrated devices includes while physically stressing the first set of devices, providing electrical power to the first set of devices and receiving electrical response data from the first set of devices, determining a second set of devices from the first set of devices, in response to the electrical response data, picking and placing the second set of devices into a transport tape media.

Abstract: A method for a MEMS device includes receiving a diced wafer having a plurality devices disposed upon an adhesive substrate and having an associated known good device data, removing a first set of devices from the plurality of devices from the adhesive substrate in response to the known good device data, picking and placing a first set of the devices into a plurality of sockets within a testing platform, testing the first set of integrated devices includes while physically stressing the first set of devices, providing electrical power to the first set of devices and receiving electrical response data from the first set of devices, determining a second set of devices from the first set of devices, in response to the electrical response data, picking and placing the second set of devices into a transport tape media.

Abstract: A method for a MEMS device includes receiving a diced wafer having a plurality devices disposed upon an adhesive substrate and having an associated known good device data, removing a first set of devices from the plurality of devices from the adhesive substrate in response to the known good device data, picking and placing a first set of the devices into a plurality of sockets within a testing platform, testing the first set of integrated devices includes while physically stressing the first set of devices, providing electrical power to the first set of devices and receiving electrical response data from the first set of devices, determining a second set of devices from the first set of devices, in response to the electrical response data, picking and placing the second set of devices into a transport tape media.

Abstract: A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

Abstract: A method for a MEMS device includes receiving a diced wafer having a plurality devices disposed upon an adhesive substrate and having an associated known good device data, removing a first set of devices from the plurality of devices from the adhesive substrate in response to the known good device data, picking and placing a first set of the devices into a plurality of sockets within a testing platform, testing the first set of integrated devices includes while physically stressing the first set of devices, providing electrical power to the first set of devices and receiving electrical response data from the first set of devices, determining a second set of devices from the first set of devices, in response to the electrical response data, picking and placing the second set of devices into a transport tape media.

Abstract: A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

Abstract: A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

Abstract: A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

Abstract: A method for fabricating a MEMS sensor device. The method can include providing a substrate, forming an IC layer overlying the substrate, forming an oxide layer overlying the IC layer, forming a metal layer coupled to the IC layer through the oxide layer, forming a MEMS layer having a pair of designated sense electrode portions and a designated proof mass portion overlying the oxide layer, forming a via structure within each of the designated sense electrode portions, and etching the MEMS layer to form a pair of sense electrodes and a proof mass from the designated sense electrode portions and proof mass portions, respectively. The via structure can include a ground post and the proof mass can include a sense comb. The MEMS sensor device formed using this method can result is more well-defined edges of the proof mass structure.

Abstract: A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

Abstract: A dynamic memory structure is disclosed. The dynamic memory structure includes: a substrate; a first strip semiconductor material disposed on the substrate and extending along a first direction; a gate standing astride the first strip semiconductor material, extending along a second direction and dividing the first strip semiconductor material into a first source terminal, a first drain terminal and a first channel region; a first dielectric layer sandwiched between the gate and the first strip semiconductor material; a first capacitor unit disposed on the substrate and comprising the first source terminal serving as a bottom electrode, a second dielectric layer covering the first source terminal to serve as a capacitor dielectric layer and a capacitor metal layer covering the second dielectric layer to serve as a top electrode. Preferably, the first source terminal and the first drain terminal have asymmetric shapes.

Abstract: A dynamic memory structure includes a strip semiconductor material disposed on a substrate, a gate standing astride the strip semiconductor material and dividing the strip semiconductor material into a source terminal, a drain terminal and a channel region wherein a source width of the source terminal is larger than or equal to a channel width, a dielectric layer sandwiched between the gate and the strip semiconductor material, and a capacitor unit disposed on the substrate and including the source terminal serving as a lower electrode.