Abstract: A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.

Abstract: A sewing machine includes a main body and a quick release needle plate module. The main body includes a base seat having an inner frame, and an outer case that is mounted to the inner frame and that defines an accommodating compartment. The quick release needle plate module includes a catch member, and a needle plate that covers the accommodating compartment, that is detachably pivoted to a rear section of the inner frame, and that engages the catch member. The quick release needle plate module further includes a press member inserted through the outer case and the inner frame, and operable to push the catch member to disengage the catch member. The needle plate has a plate body that covers the accommodating compartment, and a resilient member mounted between the inner frame and the plate body for driving pivot action of the plate body away from the inner frame.

Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.

Abstract: The present application discloses a cane with seat, comprising: a cane pole, having a pole body; a pole thot and a sliding sleeve, a peripheral surface of the pole body is provided with a protruding limiting block, a top end of the pole foot is combined with a bottom end of the pole body, the sliding sleeve is slidably sleeved on the outer peripheral surface of the rod body; two chair poles, each with a pivot rod and a chair foot rod, a top of the chair foot rod is detachably inserted into a bottom end of the pivot rod, the pivot rods of the two chair poles are pivotally connected to both sides of the pole body of the cane; two chair pole elastic ropes, respectively arranged inside the corresponding chair poles; a chair cushion, a back surface of which is provided with two chair foot clips.

Abstract: A dual-purpose stick for sitting and walking, comprising a stick body with a fixed inserting hole and an elongated hole; a seat-grip cushion body with a grip portion, a cushion portion and a grip hole, the cushion portion is axially extends axially with a pivot slot, the pivot slot comprises a vertical inserting hole in a axial direction and a horizontal inserting hole in a radial direction, a pivot inserting hole is radially penetrated on an outer surface of the seat cushion portion; an elastic element, arranged in the stick body; a fixing element, inserted into the fixed inserting hole and connected with bottom end of the elastic element; a penetrating element, inserted into the pivot hole and the elongated hole, connected with top end of the elastic element. The seat-grip cushion body can be movably pivoted and positioned between an upright grip position and a horizontal seat cushion position.

Abstract: A pixel driving device includes a driving transistor, a pixel driving circuit, an optical sensor circuit, and a reset and reading circuit. Driving transistor controls a light emission device. Pixel driving circuit is connected to the driving transistor and resets according to a first sweep signal. Pixel driving circuit compensates according to a second sweep signal. Pixel driving circuit controls the driving transistor according to a driving signal to drive light emission device. Optical sensor circuit includes a node. Optical sensor circuit resets the node to a voltage level of the driving signal. Light sensing circuit performs sensing to generate a light sensing signal. Reset and reading circuit is connected to the driving transistor, the pixel driving circuit, and the optical sensor circuit. Reset and reading circuit receives a reset and reading signal so as to reset the pixel driving circuit and to read out the light sensing signal.

Abstract: A bicycle mounting mechanism and battery box assembly installed in a bicycle frame of a bicycle is provided to include a battery box and a mounting mechanism. The battery box includes an abutment recess and an opening. The mounting mechanism includes a grip and a locating component unit being connected to the bicycle frame and defining therein an accommodation chamber for accommodating the battery box. The grip is pivotally connected to the locating component unit and includes an abutment end portion and a push end portion. The abutment end portion is capable of inserting into the accommodation chamber and in engagement with the opening with a rotating of the grip. The push end portion is capable of inserting into the accommodation chamber and abuts against the abutment recess with a further rotating of the grip.

Abstract: A pixel driving device includes a capacitance, a reset circuit, a compensation circuit, a driving transistor and a first transistor. Reset circuit and compensation circuit are coupled to a first end and a second end of capacitance. First transistor is coupled between second end of driving transistor and second end of capacitance. Reset circuit resets first end of capacitance at a power supply voltage and reset second end of capacitance at a reference voltage according to a first sweep signal respectively. Compensation circuit writes a data voltage into first end of capacitance via driving transistor and second end of capacitance is maintained at reference voltage according to a second sweep signal. First transistor generates a driving voltage difference between first end and second end of capacitance according to a control signal. Driving transistor outputs a current to a luminous element according to driving voltage difference.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: A pixel driving device includes a capacitance, a reset circuit, a compensation circuit, a driving transistor and a first transistor. Reset circuit and compensation circuit are coupled to a first end and a second end of capacitance. First transistor is coupled between second end of driving transistor and second end of capacitance. Reset circuit resets first end of capacitance at a power supply voltage and reset second end of capacitance at a reference voltage according to a first sweep signal respectively. Compensation circuit writes a data voltage into first end of capacitance via driving transistor and second end of capacitance is maintained at reference voltage according to a second sweep signal. First transistor generates a driving voltage difference between first end and second end of capacitance according to a control signal. Driving transistor outputs a current to a luminous element according to driving voltage difference.

Abstract: The present disclosure, in some embodiments, relates to a method of transporting a semiconductor wafer. The method includes transferring a semiconductor wafer into a first wafer slot of a second plurality of wafer slots within an adaptive inset. The adaptive inset is arranged within an interior cavity of a wafer cassette having a first plurality of wafer slots while transferring the semiconductor wafer into the first wafer slot. The wafer cassette and the adaptive inset are transported into a loading port of a semiconductor processing tool configured to perform a fabrication process on the semiconductor wafer.

Abstract: The present disclosure, in some embodiments, relates to a wafer cassette system. The wafer cassette system includes a wafer cassette includes a first plurality of wafer slots respectively having a first width. An adaptive inset is fastened to the wafer cassette in a rigid connection. The adaptive inset includes a second plurality of wafer slots respectively having a second width that is less than the first width. The second plurality of wafer slots are configured to receive a substrate after the adaptive inset has been fastened to the wafer cassette.

Abstract: A pixel circuit including a driving transistor, a light emission element, a compensation circuit, a storage capacitor, and a writing circuit is provided. The light emission control circuit is configured to selectively conduct the light emission element to the driving transistor. The compensation circuit is coupled with the light emission control circuit and a control terminal of the driving transistor, and is configured to form a diode-connected structure with the driving transistor. The storage capacitor includes a first terminal and a second terminal. The first terminal of the storage capacitor is coupled with the control terminal of the driving transistor, and the light emission control circuit is configured to selectively conduct the second terminal of the storage capacitor to a first power terminal. The writing circuit is configured to provide different voltages to the first terminal of the storage capacitor and the second terminal of the storage capacitor.

Abstract: A display device includes a driving circuit and a control circuit. The driving circuit is configured to receive a data voltage in response to a scanning signal, and to control the brightness of a light emitting element according to the data voltage. The control circuit is configured to provide a stop signal to the driving circuit in response to a digital signal and the scanning signal, so as to stop the light emitting element from emitting light, and in turn control the light emission period of the light emitting element.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: A pixel circuit including a driving transistor, a light emission element, a compensation circuit, a storage capacitor, and a writing circuit is provided. The light emission control circuit is configured to selectively conduct the light emission element to the driving transistor. The compensation circuit is coupled with the light emission control circuit and a control terminal of the driving transistor, and is configured to form a diode-connected structure with the driving transistor. The storage capacitor includes a first terminal and a second terminal. The first terminal of the storage capacitor is coupled with the control terminal of the driving transistor, and the light emission control circuit is configured to selectively conduct the second terminal of the storage capacitor to a first power terminal. The writing circuit is configured to provide different voltages to the first terminal of the storage capacitor and the second terminal of the storage capacitor.

Abstract: A display apparatus includes a pixel array, a plurality of gate lines and a plurality of de-load lines. The pixel array includes a plurality of display rows, each of the display rows includes a plurality of pixel circuits, and each of the pixel circuits includes a first transistor and a second transistor coupled in series between a data line and a display pixel. A control end of the first transistor of each of the pixel circuits is coupled to one of the gate lines for receiving a gate driving signal. A control end of the second transistor of each of the pixel circuits is coupled to one of the de-load lines for receiving a de-loading signal. Where an enable time period of the de-loading signal received by each of the pixel circuits covers an enable time period of the gate driving signal received by each of the pixel circuits.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

Abstract: Power and performance of a multi-core system is managed dynamically by adjusting power table indices at runtime. Runtime statistics is measured, when an application is executed on a first core of a first type at a first operating point (OPP) in a first time period, and on a second core of a second core type at a second OPP in a second time period. A controller estimates, based on the runtime statistics, a first pair of indices associated with a first OPP for the first core and a second pair of indices associated with a second OPP for the second core. During runtime, the controller incorporates the first pair of indices and the second pair of indices into power table indices; and determines, from the power table indices, selected indices associated with a selected OPP of a core of a selected core type for executing the application.