Abstract: A representative display system includes: a pixel array having a plurality of pixels, gate lines, and data lines; a first of the pixels having a first TFT, a second TFT, a storage capacitor, and an LED; the first TFT having a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode coupled to a first of the gate lines, the first source electrode and the first drain electrode coupled between a first of the data lines and a first terminal of the storage capacitor; the second TFT having a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode coupled between the first TFT and the storage capacitor; the LED coupled to the second TFT; wherein the storage capacitor is configured to store a data voltage corresponding to a data signal, coupled to the first terminal, from the first of the data lines during an on-time of the first TFT; and wherein the LED is controllable to emit light at a brightness corresponding to duratio

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

Abstract: The present disclosure, in some embodiments, relates to a wafer cassette system. The wafer cassette system includes a wafer cassette includes a first plurality of wafer slots respectively having a first width. An adaptive inset is fastened to the wafer cassette in a rigid connection. The adaptive inset includes a second plurality of wafer slots respectively having a second width that is less than the first width. The second plurality of wafer slots are configured to receive a substrate after the adaptive inset has been fastened to the wafer cassette.

Abstract: A display apparatus includes a plurality of pixel lines, a multiplexer, a first switch and a second switch. The pixel lines are respectively coupled to a plurality of data lines. The data lines include a first selected data line, a second selected data line and a plurality of other data lines. The first switch is coupled between the first selected data line and a first non-selected data line among the other data lines and is turned on or turned off according to a first control signal. The second switch is coupled between the first selected data line and a second non-selected data line among the other data lines and is turned on or cut off according to a second control signal.

Abstract: A display driving circuit is provided. The display driving circuit includes: at least one gate driving circuit, each of the at least one gate driving circuit generating a driving signal so that display pixels update pixel data according to each of the driving signals; and at least two enable-selecting circuits, generating a zone start-updating signal and a zone end-updating signal according to a zone scan-control signal and the driving signals and enabling the at least one gate driving circuit of a first portion according to the zone start-updating signal and the zone end-updating signal. In this way, the at least one gate driving circuit of the first portion generates the driving signals to update part of the display pixels, and that power saving is achieved.

Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: A pixel array substrate including a substrate, a first signal line, a second signal line, a third signal line, a first active element and a conductive pattern is provided. The first signal line and the second signal line are disposed on the substrate and intersect with each other. The third signal line is disposed on the substrate and overlapped with the second signal line. The extending direction of the third signal line is parallel to the extending direction of the second signal line. The first active element is electrically connected to the first signal line. The first active element includes a semiconductor pattern, a first gate and a second gate. The semiconductor pattern is located between the first gate and the second gate. The first gate is overlapped with the second gate and connected to the third signal line. The second gate is connected to the first gate via the conductive pattern.

Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.

Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: The present disclosure, in some embodiments, relates to a method of transporting a semiconductor wafer. The method includes transferring a semiconductor wafer into a first wafer slot of a second plurality of wafer slots within an adaptive inset. The adaptive inset is arranged within an interior cavity of a wafer cassette having a first plurality of wafer slots while transferring the semiconductor wafer into the first wafer slot. The wafer cassette and the adaptive inset are transported into a loading port of a semiconductor processing tool configured to perform a fabrication process on the semiconductor wafer.

Abstract: A light-emitting device includes a substrate, a circuit array including a plurality of circuit units disposed on the substrate, a first conductive pattern, a second conductive pattern, a first wire pattern, and a second wire pattern disposed on the circuit array, and a light-emitting element disposed on one of the circuit units. The light-emitting element includes a first electrode and a second electrode respectively electrically connected to the first conductive pattern and the second conductive pattern. The second electrode is not overlapped with the first wire pattern and the second wire pattern. A manufacturing method of the light-emitting device is also provided.

Abstract: The present disclosure relates to a wafer cassette system having an adaptive inset configured to enable wafers having a first diameter to be held by a wafer cassette configured to hold wafers having a second diameter larger than the first diameter. The wafer cassette system includes a wafer cassette having a first plurality of wafer slots configured to receive one or more wafers having a first diameter. An adaptive inset is arranged in an interior cavity of the wafer cassette. The adaptive inset has a second plurality of wafer slots configured to receive one or more wafers having a second diameter that is less than the first diameter. The adaptive inset allows for the wafer cassette to hold wafers having the second diameter, thereby enabling semiconductor processing tools to processes wafer having a different diameter than those able to be held by wafer cassettes that the tools can receive.

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

Abstract: A safety walking stick includes: a stick body; a lower base, which has a top surface formed with a receiving trough; an internal holder, which is fixedly mounted in the receiving trough of the lower base; a spring, which has an end coupled to the stick body and an opposite end coupled to the internal holder. The stick body and the internal holder are spaced from each other with a gap defining a predetermined distance therebetween.

Abstract: Power and performance of a multi-core system is managed dynamically by adjusting power table indices at runtime. Runtime statistics is measured, when an application is executed on a first core of a first type at a first operating point (OPP) in a first time period, and on a second core of a second core type at a second OPP in a second time period. A controller estimates, based on the runtime statistics, a first pair of indices associated with a first OPP for the first core and a second pair of indices associated with a second OPP for the second core. During runtime, the controller incorporates the first pair of indices and the second pair of indices into power table indices; and determines, from the power table indices, selected indices associated with a selected OPP of a core of a selected core type for executing the application.

Abstract: A display panel including a pixel array, a plurality of first shift registers, a plurality of second shift registers, a plurality of first discharge circuits, and a plurality of second discharge circuits is provided. The pixel array includes a plurality of gate lines. The shift registers provide a plurality of gate signals to the gate lines. Each of the first discharge circuits receives a third gate signal to discharge a same first gate line together with the corresponding first shift register. A rising edge of the third gate signal substantially matches a falling edge of the corresponding first gate signal. Each of the second discharge circuits receives a fourth gate signal to discharge a same second gate line together with the corresponding second shift register. A rising edge of the fourth gate signal substantially matches a falling edge of the corresponding second gate signal.

Abstract: Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n?1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.

Abstract: A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening.