Abstract: The present invention provides a foldable walking stick with adjustable length and shock-proofing mechanism. The foldable walking stick includes a rod holder containing at least two interconnected rods and a handle, arranged at an upper part of the foldable stick. Each rod connected to the handle is divided into first and second rod sections, the second rod section having a flexible pulling rope and a flexible locating pin. A plurality of locating holes, are arranged on the wall of the first rod section with different heights, allowing for locking by the flexible locating pin when inserting the second rod section. A tapered locating section is arranged onto the flexible locating pin. An inner space, is arranged onto the preset location of a rod. There is a shock-proofing mechanism, assembled within the inner space; and a grounding portion, arranged at bottom of either rod.

Abstract: A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.

Abstract: A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.

Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.

Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.

Abstract: The present invention discloses a speed adjustment system and method for performing the same, which is capable to provide different power saving behaviors adaptive for different applications (e.g. a mobile or a normal configuration) and/or different-corner-process chips. The speed adjustment system includes a reference speed generator for pre-storing multiple reference speed value, an operating speed generator for pre-storing multiple operating speed value, a comparing unit for determining whether a predefined logical operational relationship is satisfied with the operating speed value and reference speed value, a voltage controller based on said determination result to vary the operating voltage, and a speed detector for detecting the operating speed value.

Abstract: In a method of mobile information services, a mobile information service device is connected to a remote information server and a telecommunications service provider so as to timely provide information to a hand-held mobile communications device. In the method, the mobile information service device searches the information server according to a filtering rule for information complying with the filtering rule, and sends a notification message to the hand-held mobile communications device through the telecommunications service provider such that the hand-held mobile communications device, after receipt of the notification message, downloads information related to the notification message from the information server, thereby achieving user convenience and ensuring information confidentiality, without incurring extra fees.

Abstract: The present invention discloses a request transmission mechanism and a method thereof capable of reducing request transmission time. The method and mechanism in accordance with the present invention allow a request to bypass unnecessary stages in a computer system by usage of a bypassing rule and a dependence controller. The dependence controller comprises a comparator capable of receiving the instruction from the dependence controller and enabling a designated bypassing path if the request is allowed to bypass. A plurality of dependence lines are connected to the dependence controller for indicating a dependent status between at least two requests. The request may be allowed to bypass a stage even though the buffer of the stage is not empty. The method and mechanism of the present invention is capable of reducing the request transmission time by determining the dependence between the requests.

Abstract: A golf club shaft is formed of an upper segment of a fiber composite material, a lower segment of a metal material, a joint connecting the upper segment and the lower segment, and a sheath of a woody material for covering the upper segment, the lower segment, and the joint.

Abstract: An aligned clock forwarding scheme of an electronic system includes a first circuit path generating an aligned clock output signal to a subsystem and a second circuit path generating an aligned data signal to the subsystem. An external clock input serves as the source of the clock signal for the aligned clock forwarding scheme. A multiplication circuit receives the external clock input and sends multiplied clock signals to control the first and second circuit paths. The two circuit paths have the same physical characteristics so that both clock output and data signals experience the same environmental effect. There is no additional skew incurred between the clock and data signals during the data transfer between the two subsystems.

Abstract: A method is provided to reduce clock skew in an integrated circuit having a number of circuit blocks, which comprises the following steps. A first source clock coupled to a clock input terminal of a first circuit block within the circuit blocks is provided, as is a second source clock coupled to a clock input terminal of a second circuit block within the circuit blocks. When the second circuit block is configured to operate in synchronization with the first circuit block, the clock input terminal of the second circuit block is switched to the first source clock, and thus both the first circuit block and the second circuit block can operate in accordance with the same first source clock.

Abstract: A receiver for a memory controller. The memory controller sends a data request signal to a memory which responds to the data request signal by sending data and a data strobe signal back to the memory controller. The receiver comprises a delay circuit receiving and delaying the data strobe signal, an emulated data strobe signal generator receiving the data request signal to generate an emulated data strobe signal, a push pointer generator generating a plurality of push pointers having priorities, receiving and responding to the emulated data strobe signal by outputting the push pointers in an order according to the priorities, and a buffer receiving and responding to the delayed data strobe signal and the push pointers by storing the data in memory addresses corresponding to the push pointers.

Abstract: A memory address remapping method is disclosed. The memory address remapping method comprises: providing a cache-related address having a tag, an associative tag, a set index and a block offset; providing a linear operator; performing a linear calculation with a first linear operator input and a second linear operator input to obtain a first output, wherein the first linear operator input is several bits picked from the set index of the cache-related address according to a quantity and a corresponding location of a plurality of bits in the location address of a memory address, such as DDR memory-related address, Rambus memory-related address, etc.

Abstract: A memory read/write arbitration method is disclosed. The memory read/write arbitration method, which is utilized in a memory controller for increasing row hit rate and decreasing the delay of memory access, comprises: providing a arbitrator; providing a read request fifo queue having command read requests; providing a write request fifo queue having command write requests; performing a judgment step for generating a priority, wherein the judgment step comprises: performing a first sub-judgment step to determine that a command read request of the command read requests has priority over a command write request of the command write requests, or the command write request can be forwarded to a second sub-judgment step under adaptive first-step conditions; performing the second sub-judgment step to determine the read request has priority over the command write request from the first sub-judgment step, or the command write request from the first sub-judgment has priority over the command read request.

Abstract: A method for dynamic random access memory (DRAM) control with adjustable page size, including the following steps. During power-up initialization, a DRAM type is identified and a page mask for the DRAM type is set. Upon receipt of a DRAM access, an adjustable page portion of an internal address for the prior DRAM access and an adjustable page portion of an internal address for a next DRAM access are respectively determined in accordance with the page mask. A first portion of the internal address for the prior DRAM access is compared to a first portion of the internal address for the next DRAM access, and the adjustable page portion of the internal address for the prior DRAM access is compared to the adjustable page portion of the internal address for the next DRAM access, to determine whether the next DRAM access is a page hit or miss.

Abstract: A receiver for a memory controller. The memory controller sends a data request signal to a memory which responds to the data request signal by sending data and a data strobe signal back to the memory controller. The receiver comprises a delay circuit receiving and delaying the data strobe signal, an emulated data strobe signal generator receiving the data request signal to generate an emulated data strobe signal, a push pointer generator generating a plurality of push pointers having priorities, receiving and responding to the emulated data strobe signal by outputting the push pointers in an order according to the priorities, and a buffer receiving and responding to the delayed data strobe signal and the push pointers by storing the data in memory addresses corresponding to the push pointers.

Abstract: An aligned clock forwarding scheme of an electronic system includes a first circuit path generating an aligned clock output signal to a subsystem and a second circuit path generating an aligned data signal to the subsystem. An external clock input serves as the source of the clock signal for the aligned clock forwarding scheme. A multiplication circuit receives the external clock input and sends multiplied clock signals to control the first and second circuit paths. The two circuit paths have the same physical characteristics so that both clock output and data signals experience the same environmental effect. There is no additional skew incurred between the clock and data signals during the data transfer between the two subsystems.

Abstract: A method is provided to reduce clock skew in an integrated circuit having a number of circuit blocks, which comprises the following steps. A first source clock coupled to a clock input terminal of a first circuit block within the circuit blocks is provided, as is a second source clock coupled to a clock input terminal of a second circuit block within the circuit blocks. When the second circuit block is configured to operate in synchronization with the first circuit block, the clock input terminal of the second circuit block is switched to the first source clock, and thus both the first circuit block and the second circuit block can operate in accordance with the same first source clock.

Abstract: All memory commands are classified into two categories: background commands and foreground commands, depending on whether they are data related or not. The pointed background command and foreground commands are issued onto the DRAM bus at the earliest time when the required constrains are met. The background and foreground FSM controllers work in a pipelined or overlapped manner.

Abstract: A method and apparatus for refreshing dynamic memory is provided. The apparatus includes an ahead refresh controller having an ahead queue for refreshing dynamic random access memory (DRAM) when the memory request bus is idle. In such a way that no dynamic RAM bandwidth is wasted. The apparatus also comprises a normal refresh controller having a normal queue. Giving the normal refresh request in the normal priority unless the normal queue is full. The present invention allows the refresh cycles to gather on the basis of events to minimize the overheads. In other words, even when the system is running in peak performance, the normal refresh controller can largely compact the refresh cycles by means of the normal queue to decrease occurrence of interruption.