Abstract: Some embodiments regard a method comprising: using an input voltage to generate an output voltage having a first voltage level; in a first period, when the output voltage changes from the first voltage level to a second voltage level, storing electrical charges resulted from the output voltage changing from the first voltage level to the second voltage level; and in a second period subsequent to the first period when the output voltage demands energy, using a voltage generated from the stored electrical charges in place of the input voltage to generate the output voltage.

Abstract: A circuit comprises a first switch, a second switch, a third switch, and a fourth switch. Each has a first end and a second end. The circuit also comprises a capacitive device having a first capacitive end and a second capacitive end, and a voltage source. A first node having a first voltage is coupled to the first fourth-switch end, to the first second-switch end, and to the first capacitive end. A second node having a second voltage is coupled to the voltage source, to the second fourth-switch end, and to the second third-switch end. A third node is coupled to the second second-switch end, and to the first first-switch end. The first switch and the second switch are controlled such that the first node and the voltage source selectively provide the second voltage.

Abstract: Some embodiments regard a method comprising: using an input voltage to generate an output voltage having a first voltage level; in a first period, when the output voltage changes from the first voltage level to a second voltage level, storing electrical charges resulted from the output voltage changing from the first voltage level to the second voltage level; and in a second period subsequent to the first period when the output voltage demands energy, using a voltage generated from the stored electrical charges in place of the input voltage to generate the output voltage.

Abstract: A single-inductor multiple-output power converter includes an inductor having a first terminal and a second terminal. The first terminal of the inductor is coupled to a power input terminal, and the second terminal of the inductor is switched to either of the first terminal of the inductor, multiple power output terminals, and a ground terminal. By switching the second terminal of the inductor between the first terminal of the inductor, the power output terminals, and the ground terminal, the power converter may provide multiple output voltages at the power output terminals respectively, in a less loss and thereby higher efficiency manner.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a carbon and fluorine containing material. There is then formed over the oxygen containing plasma etchable layer a mask layer. There is then etched through use an oxygen containing plasma etch method while employing the mask layer as an etch mask layer the oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etched layer, where the oxygen containing plasma etch method employs an etchant gas composition comprising an oxygen containing etchant gas and a fluorine containing etchant gas.

Abstract: A new method of etching metal lines without polymer residue using a composite hard mask and two-step hard mask etching process is described. An insulating layer is provided on a semiconductor substrate. A first barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A second barrier metal layer is deposited overlying the metal layer. A composite hard mask layer is deposited overlying the second barrier metal layer. A photoresist mask is formed overlying the composite hard mask layer having openings where openings are to be made within the metal layer. First, the composite hard mask layer is partially etched away where it is not covered by the photoresist mask. Second, most of the composite hard mask layer is overetched away leaving a patterned hard mask and a portion of the hard mask layer within the openings whereby a polymer is formed within the openings.

Abstract: A process for removal of residual silicon oxide hardmask used to etch vias in low-k organic polymer dielectric layers is described. The hardmask deteriorates by developing an angular aspect or faceting along the pattern edges when used to etch organic polymer layers in an oxygen/inert gas plasma in a high density plasma etcher. In addition the deterioration of the hardmask during organic polymer etching causes a significant degradation of surface planarity which would result in via-to-via shorts when a second metal layer is patterned over it if the hardmask were left in place. The residual hardmask is selectively removed immediately after the via etch by a soft plasma etch which restores surface planarity and removes via edge facets. The plasma etch has a high selectivity of oxide-to-organic polymer so that the surface irregularities are not transferred to the polymer surface and the exposed metal surface at the base of the via is also unscathed.

Abstract: A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a material which is also susceptible to etching within a fluorine containing plasma. There is then formed upon the oxygen containing plasma etchable layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while simultaneously reaching the oxygen containing plasma etchable layer and while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching the hard mask material.

Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresists layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.