Abstract: A left and right feet pedaling analysis system is disclosed, comprising a pedaling sensing device and an electronic carrier, wherein the pedaling sensing device includes one or more transmission units and one or more accelerometers which are applied to detect the acceleration change data during pedaling, and the pedaling sensing device or/and the electronic carrier can analyze the signals coming from the accelerometer during riding the bicycle in order to acquire the pedaling rotation number, the ratio of the left and right foot forces as well as the installation direction thereby understanding the pedaling distribution ratio of the left and right foot when riding; as such, it can help improve the pedaling skills and adjust the pedaling force mode so as to reduce the risk of injury caused by excessively unbalanced pedaling asymmetry.

Abstract: A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.

Abstract: A non-volatile memory and its reading method are provided. The reading method includes: erasing a plurality of memory cells in a memory cell string; setting a target memory cell of the memory cells, setting an initial voltage, generating a plurality of programming voltages by gradually increasing the initial voltage based on a step value, sequentially performing a plurality of programming operations by the target memory cell according to the programming voltages, and verifying the target memory cell to obtain a first verifying current during the programming operations; setting a corresponding programming voltage as a target voltage through determining the first verifying current and a first reference current; and performing the programming operations on the memory cells other than the target memory cell according to the target voltage and setting the memory cell string as a reading reference memory cell string.

Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.

Abstract: An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.

Abstract: A recirculating gradient power system includes a motion carrier, a counterweight, power cylinders and a control module. A central vertical axis of the motion carrier has a rotating shaft pivotally connected with the counterweight. The power cylinders connected with a pressure source are evenly arranged at diagonal corners around the periphery of the central vertical axis. The control module connected with the power cylinders controls operation of the power cylinders which are set in advance when the counterweight is rotationally displaced to a predetermined stroke. The pressure source sequentially provides compressed gas fluid to the power cylinders to make the motion carrier continuously change its tilt orientation and tilt angle, thus forming a virtual continuous gradient. The counterweight is rotationally displaced from a high point of the motion carrier toward a lower point of the motion carrier about the rotating shaft by gravity, and the rotating shaft rotates continuously.

Abstract: An inherent information generating device adapted to an integrated circuit includes a plurality of pairs of source memory cells and a comparison circuit. One of the pairs of source memory cells includes a first source memory cell with a first electrical parameter value and a second source memory cell with a second electrical parameter value. The comparison circuit, coupled to the pairs of source memory cells and configured to generate inherent information of the integrated circuit, includes a first comparator. The first comparator is coupled to the first and second source memory cells, and is configured to compare the first electrical parameter value with the second electrical parameter value, and generate the bit value of a first bit of the inherent information according to the comparison result.

Abstract: An inherent information generating device adapted to an integrated circuit includes a plurality of pairs of source memory cells and a comparison circuit. One of the pairs of source memory cells includes a first source memory cell with a first electrical parameter value and a second source memory cell with a second electrical parameter value. The comparison circuit, coupled to the pairs of source memory cells and configured to generate inherent information of the integrated circuit, includes a first comparator. The first comparator is coupled to the first and second source memory cells, and is configured to compare the first electrical parameter value with the second electrical parameter value, and generate the bit value of a first bit of the inherent information according to the comparison result.

Abstract: A semiconductor memory device includes programmable resistance memory cells and a controller which applies a forming pulse to first and second groups of the programmable resistance memory cells for inducing a change in the first group from an initial resistance range to an intermediate resistance range, and for inducing the second group having a resistance outside the intermediate range. When a forming rate is lower than a first forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the first forming threshold rate. When a forming rate is higher than the first forming threshold rate but lower than a second forming threshold rate, the controller adjusts the forming pulse until the forming rate is higher than the second forming threshold rate. The controller applies a programming pulse to the first and second groups and generates a chip ID of the semiconductor memory device.

Abstract: A recirculating gradient power system includes a motion carrier capable of changing its tilt orientation and tilt angle. The central vertical axis of the motion carrier is provided with a rotating shaft. The rotating shaft is pivotally connected with a counterweight. The counterweight is rotationally displaced from a high point of the motion carrier toward a lower point of the motion carrier about the rotating shaft by gravity. At least four power cylinders are evenly arranged at four diagonal corners around the periphery of the central vertical axis of the motion carrier to drive the motion carrier to change the tilt orientation and the tilt angle. A control module is connected with the power cylinders for controlling the operation of the power cylinders which are set in advance when the counterweight is rotationally displaced to a predetermined stroke.

Abstract: A semiconductor device includes: a physical parameter sensing circuit configured to sense a variation of a physical parameter; an applying parameter generating circuit coupled to the physical parameter sensing circuit, configured to adjust an applying parameter from the variation of the physical parameter based on a transfer function which defines relationship between the physical parameter and the applying parameter; and a main circuit, coupled to the physical parameter sensing circuit and the applying parameter generating circuit, wherein the applying parameter generated by the applying parameter generating circuit is used to compensate effect on operations of the main circuit caused by the variation of the physical parameter.

Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.

Abstract: A semiconductor device includes: a physical parameter sensing circuit configured to sense a variation of a physical parameter; an applying parameter generating circuit coupled to the physical parameter sensing circuit, configured to adjust an applying parameter from the variation of the physical parameter based on a transfer function which defines relationship between the physical parameter and the applying parameter; and a main circuit, coupled to the physical parameter sensing circuit and the applying parameter generating circuit, wherein the applying parameter generated by the applying parameter generating circuit is used to compensate effect on operations of the main circuit caused by the variation of the physical parameter.

Abstract: A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory cell includes a first electrode, a second electrode and a memory film between the first electrode and the second electrode. The first electrode includes a bottom electrode portion and a sidewall electrode portion extending upwardly from the bottom electrode portion and between the memory film and the bottom electrode portion. A width of the sidewall electrode portion and a width of the memory film are smaller than a width of the bottom electrode portion.

Abstract: A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state.

Abstract: A timing device is provided. The timing device includes a memory device and a processor. The memory device has a first electrical parameter. The processor is configured to sense an initial value of a first electrical parameter of the memory device. The processor is configured to sense a first value of the first electrical parameter of the memory device after a first time period. And the processor is further configured to calculate the first time period according to the initial value of the first electrical parameter and the first value of the first electrical parameter.

Abstract: An array structure includes: a plurality of first signal lines and a plurality of sub-arrays. Each of the sub-array includes: a second signal line, a plurality of third signal lines, a plurality of fourth signal lines, a plurality of local decoders at each intersection of the first signal lines, the second signal line and the third signal lines; and a plurality of array cells at each intersection of the first signal lines, the third signal lines and the fourth signal lines. Respective control terminals of the local decoders are implemented by the first signal lines. In response to a selection status of the first signal lines and the second signal line, one of the local decoders selects one of the third signal lines.

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.