Abstract: A pixel circuit includes a driving transistor, a light-emitting device, a compensation sub-circuit, and a coupling sub-circuit; a first electrode of the driving transistor is coupled with a first power supply end and is configured to generate a driving current on the basis of a data voltage; the first power supply end is written with the data voltage and a first power supply voltage in a time-sharing manner; the compensation sub-circuit is coupled with a gate of the driving transistor and a second electrode of the driving transistor and is configured to connect the gate of the driving transistor and the second electrode of the driving transistor in response to a signal of a scan signal end; the coupling sub-circuit is coupled with the gate of the driving transistor; and the light-emitting device emits light under the action of the driving current.

Abstract: A display substrate includes a drive circuit layer disposed on a substrate. The drive circuit layer includes a plurality of circuit units, The plurality of circuit units include a pixel drive circuit, at least one normal circuit unit, and at least one tracing circuit unit. The at least one normal circuit unit includes a first compensation line extending along a first direction and at least one second compensation line extending along a second direction, and the first direction intersects with the second direction. The first compensation line and the at least one second compensation line intersect with each other and form an integrated structure.

Abstract: The invention discloses a shift register, a driving method thereof, a display substrate and a display device. The shift register includes a cascade output sub-circuit and a scan output sub-circuit; the cascade output sub-circuit is configured to provide signals to a first node and a second node under controlling of signals from a signal input terminal, a first clock signal terminal and a second clock signal terminal, and to provide a signal at a first power supply terminal or a second power supply terminal to a cascade output terminal under controlling of signals from the first node and the second node; the scan output sub-circuit is configured to provide a signal from a first power supply terminal or a second power supply terminal to a scan output terminal under controlling of signals from a first node, a second node and a scan control signal terminal.

Abstract: A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises multiple first regions and second regions alternately arranged; in the direction perpendicular to the display substrate, a display region comprises a driving structure layer and a light-emitting structure layer; a driving structure layer of each first region comprises multiple pixel driving circuits, a driving structure layer of each second region comprises at least one gate driving apparatus and/or at least one signal wire, a light-emitting structure layer of each first region comprises multiple first light-emitting devices, a light-emitting structure layer of each second region comprises multiple second light-emitting devices; at least one first light-emitting device in each first region is connected to at least one pixel driving circuit in first region, and at least one second light-emitting device in each second region is connected to at least one pixel driving circuit in first region.

Abstract: A display substrate, a working method thereof, and a display device are provided. The display substrate includes K pixel rows and K is a positive integer greater than 1; at least one pixel row includes an initial signal line, a scan signal line, and a plurality of sub-pixels disposed sequentially along an extension direction of the initial signal line and the scan signal line; the initial signal line includes a third initial signal line, the scan signal line includes a second scan signal line, at least one sub-pixel includes a pixel drive circuit, the pixel drive circuit at least includes a third transistor as a drive transistor and an eighth transistor as an initialization transistor; in at least a pixel row, the eighth transistor is connected with the third initial signal line, the second scan signal line, and a second electrode of the drive transistor.

Abstract: An array substrate includes: a substrate; a plurality of pixel circuits disposed on the substrate; a first conductive layer including a plurality of conductive patterns; and a second conductive layer disposed on a side of the first conductive layer away from the substrate and including a plurality of first signal lines. The plurality of pixel circuits being arranged in rows and columns. The plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and a conductive pattern includes at least two contact portions arranged at intervals. The plurality of first signal lines are arranged at intervals in a first direction and all extend in a second direction; a first signal line is electrically connected to at least one conductive pattern, and the first signal line is connected to the at least two contact portions of the conductive pattern.

Abstract: The present disclosure relates to a display panel, including: an array substrate; and a light-emitting layer located on a side of the array substrate and including a plurality of light-emitting units, wherein each light-emitting unit includes an anode block, a light-emitting functional layer, and a cathode block stacked in sequence in a direction away from the array substrate; wherein the light-emitting layer includes a cathode layer, and the cathode layer includes a plurality of cathode blocks distributed at intervals.

Abstract: A display panel includes a pixel driving circuit including a first type transistor and a second type transistor, the display panel further includes a base substrate, a first active layer located on a side of the base substrate, a second active layer located on the side of the first active layer away from the base substrate, a first conductive layer located between the first active layer and the second active layer; at least partial structure of the first active layer is used to form a channel region of the first type transistor; at least partial structure of the second active layer is used to form the channel region of the second type transistor; partial structure of the first conductive layer is used to form the gate of the first type transistor, partial structure of the first conductive layer is used to form the bottom gate of the second type transistor.

Abstract: Disclosed is a display substrate including a display region (100) and a bonding region (200) located on a side of the display region (100). The display region (100) includes a base substrate (101) and a drive circuit layer disposed on the base substrate (101). The drive circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines (60), and a plurality of data connection lines (70). The data connection lines (70) include a first connection line (71) extending along a first direction and a second connection line (72) extending along a second direction. The first connection line (71) is electrically connected with the second connection line (72) and a data signal line (60) respectively. The first connection line (71) and the second connection line (72) are located in different conductive layers.

Abstract: A display apparatus includes a plurality of first touch channels, second touch channels, first touch traces, second touch traces, and a first touch chip and second touch chip. At least one first touch channel and second touch channel are arranged in each sub-region, and the at least one first touch channel and second touch channel are arranged crosswise and insulated from each other; first touch channels located in different sub-regions are insulated from each other, and second touch channels located in different sub-regions are insulated from each other. In any two sub-regions, first touch traces connected to first touch channels and second touch traces connected to second touch channels are connected to the first touch chip; in remaining two sub-regions except the any two sub-regions, first touch traces connected to first touch channels and second touch traces connected to second touch channels are connected to the second touch chip.

Abstract: A shift register unit includes a first output transistor, a gate driving signal output end, a first output control node, a control signal input end and a first signal input end. The first output transistor includes a dual-gate structure, a first gate electrode of the first output transistor is coupled to the first output control node, a second gate electrode of the first output transistor is coupled to the control signal input end, a first electrode of the first output transistor is coupled to the first signal input end, and a second electrode of the first output transistor is coupled to the gate driving signal output end.

Abstract: A display substrate includes a plurality of pixel driving circuits and data signal line groups. A column of pixel driving circuits are divided into n pixel driving circuit groups, and a data signal line group is electrically connected to a column of pixel driving circuits. Two data signal line groups respectively electrically connected to an m-th column of pixel driving circuits and an (m+1)-th column of pixel driving circuits include a first data signal line and a second data signal line, located between the two columns of pixel driving circuits. Multiple anode transfer lines electrically connected to the (m+1)-th column of pixel driving circuits include a first anode transfer line including a first anode transfer portion in a same layer as a data signal line. In a row direction, the first anode transfer portion is located between the first data signal line and the second data signal line.

Abstract: An array substrate includes a substrate and pixel circuits disposed on the first substrate. A pixel circuit includes a first light-emitting control transistor and a second light-emitting control transistor. The array substrate further includes a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control signal line is electrically connected to a gate of the first light-emitting control transistor. The second light-emitting control signal line is electrically connected to a gate of the second light-emitting control transistor. The array substrate further includes conductive layers. The first light-emitting control signal line and the second light-emitting control signal line are electrically insulated. The first light-emitting control signal line and the second light-emitting control signed line are located in different conductive layers.

Abstract: Provided is display panel. The display panel has a display region, an aperture region, and a peripheral region, the peripheral region being disposed around the aperture region, and the display region surrounding the peripheral region; wherein the display panel comprises: a substrate, disposed within the display region and the peripheral region; an inorganic insulating layer, disposed on a side of the substrate, and extending from the display region to the peripheral region; a plurality of conductive isolation pillars; an insulative isolation layer; an organic material layer; and a first electrode, disposed on a side, away from the substrate, of the organic material layer and extending from the display region to the peripheral region.

Abstract: The display panel has a display area and a peripheral area outside the display area; the display area is provided with pixel circuits; the peripheral area is provided with a peripheral circuit; at least one peripheral circuit includes a plurality of circuit groups spaced apart along a column direction, a trigger signal line, and at least one test line; one of the circuit groups includes a plurality of shift registers cascaded along the column direction; any row of the pixel circuits is connected to at least one of the shift registers through a scanning line; a first shift register of each circuit group is connected to one trigger signal line, and there are different trigger signal lines connected to different circuit groups; a last shift register of at least one of the circuit groups is connected to one test line.

Abstract: A pixel circuit includes a driving circuit, a first light emitting control circuit and a light emitting element; a first terminal of the driving circuit is electrically connected to a second node, a second terminal of the driving circuit is electrically connected to a first voltage line, and the driving circuit is configured to control to generate a driving current under the control of a potential of the first node; the first light emitting control circuit is configured to control to connect or disconnect the first electrode of the light emitting element and the second voltage line under the control of the first light emitting control signal; or, the first light emitting control circuit is configured to control to connect or disconnect the second electrode of the light emitting element and the second node under the control of the first light emitting control signal.

Abstract: A driving circuit, a driving method and a display apparatus. The driving circuit comprises a first node control circuit, a first control circuit, a second control circuit, an output node control circuit, a first energy storage circuit and an output circuit; the first control circuit controls the connection or disconnection between a second node and a first voltage line under the control of a setting control signal; the second control circuit controls the connection or disconnection between the second node and a second voltage line under the control of a first clock signal and a potential of the second node; and the output node control circuit controls the connection or disconnection between the second node and a first output node under the control of the first clock signal.

Abstract: A driving circuit, a driving method, a pixel circuit, a display panel and a display device are provided. The driving circuit includes a first switching circuit and a scanning signal generation circuit. The first switching circuit writes a data signal provided by a data output end into the scanning signal generation circuit under the control of a first gating control signal. The scanning signal generation circuit generates a scanning signal in accordance with the data signal, and outputs the scanning signal through a scanning signal output end.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate, sub-pixels, a pixel defining layer having openings, spacers on the pixel defining layer. A shape of at least one of the openings is a polygon with at least one vertex angle cut off, and a corner portion of the opening includes a first corner portion formed by cutting off one vertex angle included between two sides of the polygon from the polygon. At least one of the spacers is arranged at an interval between the first corner portion and the opening adjacent to the first corner portion, and a connecting line between a geometric center of the opening where the first corner portion is located and a geometric center of the opening adjacent to the first corner portion passes through the first corner portion and the spacer.

Abstract: A driving circuit, a driving method, a driving module, and a display device are provided. The driving circuit includes a first output circuit, a second output circuit, and a first output node control circuit. The first output circuit controls a driving signal output end to be electrically connected to or electrically disconnected from a first voltage end under the control of a potential of a first output node. The second output circuit controls the driving signal output end to be electrically connected to or electrically disconnected from an output signal end under the control of a potential of a second output node. The first output node control circuit controls the first output node to be electrically connected to or electrically disconnected from a second voltage end under the control of a first output control signal.