Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.

Abstract: A camera driving module includes: a base including a central opening; a casing disposed on the base and including an opening hole corresponding to the central opening; a lens unit movably disposed on the casing; and a focus driving part. The focus driving part includes a carrier, an AF coil element, at least two permanent magnets and a Hall element. The carrier is disposed on the lens unit and movable in a direction parallel to an optical axis. The AF coil element is fixed to the base and faces toward the carrier. The permanent magnets are fixed on one side of the carrier facing toward the base and disposed opposite to each other about the optical axis. The Hall element faces toward a corresponding surface of one of the permanent magnets. The AF coil element and the corresponding surfaces are arranged in the direction parallel to the optical axis.

Abstract: A camera module includes a plastic carrier, an imaging lens assembly, a reflective element and a plurality of auto-focusing elements. The plastic carrier includes an inner portion and an outer portion, wherein an inner space is defined by the inner portion, and the outer portion includes at least one mounting structure. The imaging lens assembly is disposed in the inner space of the plastic carrier. The reflective element is for folding an image light by a reflective surface of the reflective element into the imaging lens assembly. The auto-focusing elements include at least two magnets and at least one wiring element, wherein the auto-focusing elements are for moving the plastic carrier along a second optical axis of the imaging lens assembly, and the magnets or the wiring element can be disposed on the mounting structure of the outer portion.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.

Abstract: A semiconductor package including one or more heat dissipation systems and a method of forming are provided. The semiconductor package may include one or more integrated circuit dies, an encapsulant surrounding the one or more integrated circuit dies, a redistribution structure over the one or more integrated circuit dies and the encapsulant. The redistribution structure may include one or more heat dissipation systems, which are electrically isolated from remaining portions of the redistribution structure. Each heat dissipation system may include a first metal pad, a second metal pad, and one or more metal vias connecting the first metal pad to the second metal pad.

Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

Abstract: A semiconductor device package is provided. The semiconductor device package includes a semiconductor device, a molding material surrounding the semiconductor device, and a conductive slot positioned over the molding material. The conductive slot has an opening and at least two channels connecting the opening to the edges of the conductive slot, and at least two of the channels extend in different directions.

Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via.

Abstract: A device includes a first redistribution structure comprising a first conductive line and a second conductive line. An integrated circuit die is attached to the first redistribution structure. A first via is coupled to the first conductive line on a first side, and a first conductive connector is coupled to the first conductive line on a second side opposite the first side. A second via is coupled to the second conductive line on the first side, and a second conductive connector is coupled to the second conductive line on the second side. The first via directly contacts the first conductive line without directly contacting the first conductive connector. The second via directly contacts the second conductive line and directly contacts the second conductive connector.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.

Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A method includes forming a plurality of first conductive vias over a redistribution layer (RDL); disposing a first die over the RDL and adjacent to the first vias; and forming a plurality of second conductive vias over and electrically connected to the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias. The method further includes forming a plurality of third conductive vias over the first die; disposing a second die over the first die and adjacent to the third conductive vias; and encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias with a molding material.

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Abstract: A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.