Patents by Inventor Ming-Hung Tseng
Ming-Hung Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200090855Abstract: A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.Type: ApplicationFiled: November 25, 2019Publication date: March 19, 2020Inventors: Chen-Hua Yu, Tzu-Chun Tang, Chuei-Tang Wang, Hao-Yi Tsai, Ming Hung Tseng, Chieh-Yen Chen, Hung-Yi Kuo
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Publication number: 20200075516Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, a plurality of vias extending through the molding, and a RDL disposed over the transceiver and the plurality of vias. In some embodiments, the RDL includes an antenna disposed over and electrically connected to the transceiver, and a dielectric layer surrounding the antenna. In some embodiments, the antenna includes an elongated portion extending over the molding and a via portion electrically connected to the transceiver.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Inventors: VINCENT CHEN, HUNG-YI KUO, CHUEI-TANG WANG, HAO-YI TSAI, CHEN-HUA YU, WEI-TING CHEN, MING HUNG TSENG, YEN-LIANG LIN
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Publication number: 20200066635Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.Type: ApplicationFiled: November 1, 2019Publication date: February 27, 2020Inventors: Shih-Wei LIANG, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Hsien-Ming Tu
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Publication number: 20200013710Abstract: A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.Type: ApplicationFiled: September 13, 2019Publication date: January 9, 2020Inventors: Hao-Juin Liu, Chita Chuang, Yao-Chun Chuang, Ming Hung Tseng, Chen-Shien Chen
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Patent number: 10530175Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.Type: GrantFiled: August 9, 2016Date of Patent: January 7, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
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Publication number: 20200006259Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai, Ming Hung Tseng
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Patent number: 10510478Abstract: A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.Type: GrantFiled: May 24, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tzu-Chun Tang, Chuei-Tang Wang, Hao-Yi Tsai, Ming Hung Tseng, Chieh-Yen Chen, Hung-Yi Kuo
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Publication number: 20190371718Abstract: A method for manufacturing a semiconductor device includes following operations. A first substrate with a conductive pad is received. A connector is disposed over the conductive pad. A second substrate including a conductive land is provided. A position of the first substrate or the second substrate is adjusted thereby a geometric center of the conductive land is deviated from a geometric center of the connector in a deviated distance. The connector is bonded with the conductive land. A temperature of the semiconductor device is adjusted so as to control elongation of the first substrate and the second substrate, thereby the geometric center of the connector is substantially aligned with the geometric center of the conductive land.Type: ApplicationFiled: August 13, 2019Publication date: December 5, 2019Inventors: HUA-WEI TSENG, CHITA CHUANG, MING HUNG TSENG, CHEN-SHIEN CHEN, MIRNG-JI LII
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Patent number: 10497646Abstract: A semiconductor device includes a first molding layer; a second molding layer formed over the first molding layer; a first conductive coil including a first portion continuously formed in the first molding layer and a second portion continuously formed in the second molding layer, wherein the first and the second portions are laterally displaced from each other; and a second conductive coil formed in the second molding layer, wherein the second conductive coil is interweaved with the second portion of the first conductive coil in the second molding layer.Type: GrantFiled: July 28, 2016Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wei Liang, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Hsien-Ming Tu
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Patent number: 10475755Abstract: A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.Type: GrantFiled: October 29, 2018Date of Patent: November 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Vincent Chen, Hung-Yi Kuo, Chuei-Tang Wang, Hao-Yi Tsai, Chen-Hua Yu, Wei-Ting Chen, Ming Hung Tseng, Yen-Liang Lin
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Publication number: 20190279810Abstract: A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Inventors: Chen-Hua Yu, Tzu-Chun Tang, Chuei-Tang Wang, Hao-Yi Tsai, Ming Hung Tseng, Chieh-Yen Chen, Hung-Yi Kuo
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Publication number: 20190244935Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.Type: ApplicationFiled: April 22, 2019Publication date: August 8, 2019Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 10304614Abstract: A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.Type: GrantFiled: November 29, 2018Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tzu-Chun Tang, Chuei-Tang Wang, Hao-Yi Tsai, Ming Hung Tseng, Chieh-Yen Chen, Hung-Yi Kuo
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Publication number: 20190148301Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.Type: ApplicationFiled: February 28, 2018Publication date: May 16, 2019Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
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Patent number: 10269481Abstract: A structure includes a first encapsulating layer, and a first coil in the first encapsulating layer. A top surface of the first encapsulating layer is coplanar with a top surface of the first coil, and a bottom surface of the first encapsulating layer is coplanar with a bottom surface of the first coil. A second encapsulating layer is over the first encapsulating layer. A conductive via is in the second encapsulating layer, and the first conductive via is electrically coupled to the first coil. A third encapsulating layer is over the second encapsulating layer. A second coil is in the third encapsulating layer. A top surface of the third encapsulating layer is coplanar with a top surface of the second coil, and a bottom surface of the third encapsulating layer is coplanar with a bottom surface of the second coil.Type: GrantFiled: September 1, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tzu-Chun Tang, Chuei-Tang Wang, Hao-Yi Tsai, Ming Hung Tseng, Chieh-Yen Chen, Hung-Yi Kuo
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Patent number: 10269676Abstract: A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.Type: GrantFiled: October 4, 2012Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsien Chiang, Ming Hung Tseng, Chen-Shien Chen
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Patent number: 10269702Abstract: A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material until the coil is exposed, forming at least one dielectric layer over the encapsulating material and the coil, and forming a plurality of redistribution lines extending into the at least one dielectric layer. The plurality of redistribution lines is electrically coupled to the coil.Type: GrantFiled: September 1, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Tsung-Hsien Chiang, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
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Patent number: 10269773Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.Type: GrantFiled: October 13, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
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Publication number: 20190103379Abstract: A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.Type: ApplicationFiled: October 13, 2017Publication date: April 4, 2019Inventors: Chen-Hua Yu, Ming Hung Tseng, Yen-Liang Lin, Tzu-Sung Huang, Tin-Hao Kuo, Hao-Yi Tsai
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Publication number: 20190103370Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.Type: ApplicationFiled: January 26, 2018Publication date: April 4, 2019Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hung-Yi Kuo, Hao-Yi Tsai, Ming Hung Tseng