Abstract: The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump interconnection structure allows for optimized packaging assembly yield and bond integrity.

Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Abstract: A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

Abstract: Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die.

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

Abstract: Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.

Abstract: A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.

Abstract: A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.

Abstract: A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.

Abstract: An o-ring sealing device, molded with an imbedded piezoelectric element, for use in vacuum systems. The imbedded element, of a circumferential length, has an oblong cross-sectional shape, the oblong shape having a pair of ends for externally connecting to a signal processor. The piezoelectric element is concentrically disposed and centrally placed within a mold cavity of a predetermined diameter. The cavity is filled with an elastic material fully encapsulating and insulating the piezoelectric element.

Abstract: An o-ring sealing device, molded with an imbedded piezoelectric element, for use in vacuum systems. The imbedded element, of a circumferential length, has an oblong cross-sectional shape, the oblong shape having a pair of ends for externally connecting to a signal processor. The piezoelectric element is concentrically disposed and centrally placed within a mold cavity of a predetermined diameter. The cavity is filled with an elastic material fully encapsulating and insulating the piezoelectric element.