Abstract: A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

Abstract: A circuit and a method for maintaining the aspect ratio of images when there is a difference in format between image sources and display panels is provided. Lines are added in the vertical direction both at the top and at the bottom of the display panel in order to make the display panel have the same aspect ratio as the input image. A line enable signal is used to expand the vertical lines to maintain aspect ratio. Previously, the period of line enable signals could not be programmed to vary sufficiently to yield the necessary expansion to allow the aspect ratio of the display panel image to match the aspect ratio of the source image. This design allows the period of the line enable signal to vary enough to match all reasonable aspect ratios of input images.

Abstract: A fuse circuit for repair and detection includes a fuse resistor, a reference resistor, a voltage sensing circuit, an OP amplifier and a latch circuit. The resistance difference is correctly sensed by means of the voltage sensing circuit and the OP amplifier according to a voltage difference. Hence, whether the fuse resistor is programmed or not is accurately detected by the logic level of the output signal.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: The present invention provides a SATA cable with light display feature, which is mainly used for the SATA cables for computer host and their peripheral devices. With the light display capability, the connection readiness status and the signal transmission conditions can be easily detected via the pins on the SATA cable. The realization technique used by the present invention is adding the LED lights and the control pins inlayed at the two plug-in ends of the SATA cable. When the two plug-in ends of the SATA cable are both connected and ready, or there is data transmission going on, the control pins automatically turn on the LED lights to indicate the ON/ACTIVE connection status/condition.

Abstract: A USB portable storage device with multi-port plugs is provided, including a flash memory, a USB controller, a USB physical layer, and a plurality of USB connector. The USB controller is connected to the flash memory for controlling the access to the flash memory. The USB physical layer provides the interface between the USB controller and the USB connectors, and is connected to a plurality of USB connectors to form data communication channels with all these USB connectors.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: A particular DRAM data path architecture is disclosed. In accordance with this invention, the sharing of MDQ sense amplifiers simplifies the circuit design of the memory sub array. Fewer MDQ sense amplifiers and fewer unique MDQ lines leads to a reduced chip layout area. The high address bit of the word line row address (RA) is used to select a particular main data sense amp by means of a control switch. Not only are the sense amplifiers multiplexed for the new sub array, but the data I/O are multiplexed as well, leading to a significant reduction in the number of circuits required.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: A method for a deep power down mode is described for a memory chip in which voltage regulators and charge pumps are turned off, memory cell voltages are floated, and support circuit internal power supply voltages are replaced by voltages that are derived from the external chip voltage. Prior to being placed into a deep power down mode, all memory cells are placed into a precharge state from which the memory cell voltages are floated upon entering the deep power down mode. Pass through circuits connect externally derived voltages to the support circuit power supply voltage lines, controlled by a deep power down signal. Maintaining a voltage bias on the support circuits prevents latch up problems when the memory chip is brought out of the deep power down mode.

Abstract: The present invention relates to display adjustment and balance methods for liquid crystal displays, LCDs. A wide-range display position adjustment method is described. Compared with the prior art liquid crystal display controllers, the embodiments of this invention are not limited by the width of the vertical and horizontal front and back porch regions of the timing diagrams. These porch values are a function of the display chip technology. The display location control of this invention is independent of the limits of the front and back porch times. The embodiments of this invention facilitate the design of a display position control circuit which allows the image display to be rolled around anywhere on the panel.

Abstract: A method to generate an optimum phase shifted sampling clock for sampling a synchronized video signal A(t) having a synchronization signal SYNC pulse is achieved. The method comprises, first, generating a sampling clock having a first edge aligned with a trailing edge of the SYNC pulse. The sampling clock period comprises the SYNC pulse period divided by M. Second, the number of sampling clock cycles N is counted from the trailing edge of the SYNC pulse until the A(t) value at the first edge of the sampling clock exceeds a minimum value. Third, the sampling clock and the SYNC pulse are phase shifted forward until the A(t) value at the first edge of the sampling clock first exceeds a minimum value on clock cycle N?1 to thereby establish a worst case phase shift of the sampling clock. Finally, A(t) is sampled at an offset from the worst case phase shift to thereby generate an optimum phase shifted sampling clock.

Abstract: The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem.

Abstract: The present invention relates to display adjustment and balance methods for liquid crystal displays, LCDs. A wide-range display position adjustment method is described. Compared with the prior art liquid crystal display controllers, the embodiments of this invention are not limited by the width of the vertical and horizontal front and back porch regions of the timing diagrams. These porch values are a function of the display chip technology. The display location control of this invention is independent of the limits of the front and back porch times. The embodiments of this invention facilitate the design of a display position control circuit which allows the image display to be rolled around anywhere on the panel.

Abstract: A hierarchical bit line selection circuit is connected between a plurality of pairs of bit lines of a plurality of sub-arrays of a random access memory and a data line sense amplifier. The bit line selection circuit has a bit line selector circuit to selectively couple one pair of bit lines of the plurality of bit lines of each sub-array to the pair of local data lines. The bit line selection circuit further has a local data line selector circuit to select one of a plurality of pairs of local data lines to be connected to a pair main data lines that are connected to the inputs of the data line sense amplifier. The memory cell sub-arrays are folded in placement with the main data line switches to reduce data access time.

Abstract: A hierarchical bit line selection circuit is connected between a plurality of pairs of bit lines of a plurality of sub-arrays of a random access memory and a data line sense amplifier. The bit line selection circuit has a bit line selector circuit to selectively couple one pair of bit lines of the plurality of bit lines of each sub-array to the pair of local data lines. The bit line selection circuit further has a local data line selector circuit to select one of a plurality of pairs of local data lines to be connected to a pair main data lines that are connected to the inputs of the data line sense amplifier.

Abstract: A bolt assembly includes a bolt member, a washer, and a nut. The bolt member includes a head and a shank. The shank has a connecting section that is connected to an article confronting side of the head, an externally threaded section that extends from the connecting section, a breakable tip that extends from the externally threaded section and that is formed with a plurality of axially extending and angularly displaced teeth, and an annular groove that is formed at a juncture of the externally threaded section and the breakable tip. The washer is sleeved on the shank of the bolt member, and has an article confronting side formed with a plurality of spaced apart and radially extending anti-skid projections, and a nut confronting side opposite to the article confronting side of the washer.

Abstract: A method is designed to adjust the distance between the central axes of two ocular lenses of an optical instrument. The method involves the use of a link mechanism to actuate two movable prisms and the two ocular lenses of the optical instrument to move respectively along a base surface such that the optical axes of effective diameters of the two movable prisms are coaxial with the optical axes of the corresponding ocular lenses.

Abstract: In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.