Abstract: A magnetoresistive random access memory (MRAM) device includes a memory cell corresponding to one read bit line, one read word line, one write word line, and two or more write bit lines. The memory cell includes a first memory unit and a second memory unit each corresponding to a respective write bit line. Each of the first and second memory units comprises: a free magnetic region having a first easy axis, a pinned magnetic region having a second easy axis, and a tunneling barrier between the free magnetic region and the pinned magnetic region.

Abstract: A magnetic random access memory having reference magnetic resistance is provided. The memory includes at least one magnetic memory cell having an antiferromagnet layer, a pinned layer formed thereon, a tunnel barrier layer formed thereon, and a free layer formed thereon. The pinned layer and free layer are arranged orthogonally to form a reference magnetic resistance state. Through the provided MRAM structure, the access accuracy is greatly increased and the access speed is accelerated.

Abstract: A structure of magnetic memory cell, suitable for a magnetic memory device with toggle mode access operation is provided, which includes a magnetic pinned stacked layer as a portion of a substrate structure; a tunnel barrier layer disposed on the magnetic pinned stacked layer; a magnetic free stacked layer disposed on the tunnel barrier layer; a magnetic bias stacked layer disposed on the magnetic free stacked layer, wherein the magnetic bias stacked layer applies a compensative magnetic field to the magnetic free stacked layer, so as to move a toggle operation region towards a magnetic zero point. Further, the magnetic field effect of the magnetic bias stacked layer also includes reducing a direct mode region adjacent to the toggle operation region.

Abstract: A magnetic memory cell and a manufacturing method for the magnetic memory cell are provided. In the magnetic memory cell, a pinned layer of a magnetic bottom electrode can be formed with sizes different from the free layer. The wider magnetic bottom electrode produces a preferable uniform bias field that will create a normal magnetization vector distribution in the end domain of the free layer, and thus achieving a preferred switching property. The above process can also be achieved through self-alignment. In addition, by adjusting the bias field of the bottom electrode, uniform field distribution over entire free layer can be significantly improved, and thus the magnetic memory cell will have a very low writing toggle current.

Abstract: A current source for magnetic random access memory (MRAM) is provided, including a band-gap reference circuit, a first stage buffer, and a plurality of second stage buffers. The band-gap reference circuit provides an output reference voltage which is locked by the first stage buffer. The plurality of second stage buffers generate a stable voltage in response to the locked voltage, so as to provide a current for the conducting wire after being converted, such that magnetic memory cell changes its memory state in response to the current. The current source may reduce the discharge time under the operation of biphase current, so as to raise the operating speed. Further, the circuit area of the current source for the MRAM is also reduced. The operation of multiple write wires may be provided simultaneously to achieve parallel write.

Abstract: A method for accessing a memory cell of a magnetoresistive random access memory (MRAM) device, where the memory cell includes a plurality of memory units, includes writing the memory cell by identifying ones of the memory units having stored therein a datum different from a datum to be written thereto; and simultaneously writing all of the ones of the memory units. An MRAM device includes a plurality of write word lines, a plurality of write bit lines, and a plurality of memory cells. Each memory cell includes a plurality of memory units. Each memory unit includes a free magnetic region having one or more easy axes non-perpendicular to the write bit lines and non-perpendicular to the write word lines, a pinned magnetic region, and a tunneling barrier between the free magnetic region and the pinned magnetic region.

Abstract: Method of making an electroplated interconnection wire of a composite of metal and carbon nanotubes is disclosed, including electroplating a substrate having a conductive baseline on a surface thereof in an electroplating bath containing a metal ion and carbon nanotubes, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline. Alternatively, a method of the present invention includes preparing a dispersion of carbon nanotubes dispersed in an organic solvent, printing a baseline with the dispersion on a surface of a substrate, evaporating the organic solvent to obtain a conductive baseline, and electroplating the surface in an electroplating bath containing a metal ion, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline.

Abstract: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal layer. The multi-layered metal layer is formed by at least one metal layer, where the direction of the anisotropy axis of the antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged orthogonally. The provided memory has the advantage of lowering the switching field of the ferromagnetic layer, and further lowering the writing current.

Abstract: Method of making an electroplated interconnection wire of a composite of metal and carbon nanotubes is disclosed, including electroplating a substrate having a conductive baseline on a surface thereof in an electroplating bath containing a metal ion and carbon nanotubes, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline. Alternatively, a method of the present invention includes preparing a dispersion of carbon nanotubes dispersed in an organic solvent, printing a baseline with the dispersion on a surface of a substrate, evaporating the organic solvent to obtain a conductive baseline, and electroplating the surface in an electroplating bath containing a metal ion, so that an electroplated interconnection wire of a composite of the metal and carbon nanotubes is formed on the conductive baseline.

Abstract: The present invention relates to a structure and manufacturing process of a nano device transistor for a biosensor. The structure, the manufacturing process and the related circuit for a carbon nano tube or nano wire transistor biosensor device are provided. The refurbished nano device is used for absorbing various anti-bodies so as to detect the specific antigens or absorbing various biotins. Therefore, the object of the present invention to detect the specific species for bio measurement can be achieved.

Abstract: A method for writing a memory cell of a magnetoresistive random access memory (MRAM) device includes, sequentially, providing a first magnetic field in a first direction, providing a second magnetic field in a second direction substantially perpendicular to the first direction, turning off the first magnetic field, providing a third magnetic field in a third direction opposite to the first direction, turning off the second magnetic field, and turning off the third magnetic field. A method for switching magnetic moments in an MRAM memory cell includes providing a magnetic field in a direction forming a blunt angle with a direction of a bias magnetic field. A method for reading an MRAM device includes partially switching magnetic moments in a reference memory cell to generate a reference current; measuring a read current through a memory cell to be read; and comparing the read current with the reference current.

Abstract: A non-via method of connecting a magnetoelectric element with a conductive line. A magnetoelectric element is formed on a substrate, and spacers are formed on side walls of the magnetoelectric element. A dielectric layer is deposited over the substrate and magnetoelectric element and planarized to a level above the magnetoelectric element. The dielectric layer is etched to expose the upper surface of the magnetoelectric element, and a conductive line is formed on the magnetoelectric element.

Abstract: A magnetic random access memory with lower switching field through indirect exchange coupling. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, a metal layer formed on the ferromagnetic free layer, and a second antiferromagnetic layer formed on the metal layer. The anisotropy axis of the second antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged in parallel. The net magnetic moment of the antiferromagnetic layer interface between the second antiferromagnetic layer and the metal layer is close to zero. The memory has the advantages of lowering the switching field of the ferromagnetic layer and lowering the writing current.

Abstract: A magnetic random access memory having reference magnetic resistance is provided. The memory includes at least one magnetic memory cell having an antiferromagnet layer, a pinned layer formed thereon, a tunnel barrier layer formed thereon, and a free layer formed thereon. The pinned layer and free layer are arranged orthogonally to form a reference magnetic resistance state. Through the provided MRAM structure, the access accuracy is greatly increased and the access speed is accelerated.

Abstract: A magnetic random access memory with lower switching field is provided. The memory includes a first antiferromagnetic layer, a pinned layer formed on the first antiferromagnetic layer, a tunnel barrier layer formed on the pinned layer, a ferromagnetic free layer formed on the tunnel barrier layer, and a multi-layered metal layer. The multi-layered metal layer is formed by at least one metal layer, where the direction of the anisotropy axis of the antiferromagnetic layer and the ferromagnetic layer and that of the ferromagnetic free layer are arranged orthogonally. The provided memory has the advantage of lowering the switching field of the ferromagnetic layer, and further lowering the writing current.

Abstract: The present invention relates to a hybrid MRAM architecture, and more particularly to a hybrid MRAM architecture capable of being used with an MCU and an MPU. This hybrid MRAM architecture is adapted to a controlling device for accessing a bit of information, comprising a plurality of first MRAM arrays (1T1MTJ architecture), a plurality of second MRAM arrays (XPC architecture), an address line, an access decoder, a sensing and writing circuit, and at least one I/O bus. The access decoder accesses to the bit of information from either the first or the second MRAM arrays selected in accordance with an address signal from the controlling device. The sensing and writing circuit amplifies the bit of information and transmits it to the controlling device via the at least one I/O bus. Accordingly, the access of the bit of information is completed.

Abstract: A magnetic random access memory with tape read line, fabricating method and circuit thereof is provided. The memory is composed of a top write line, a bottom write line which is vertical to the top write line, a MTJ formed on the bottom write line, a spacer formed around the MTJ, and a tape read line formed on the MTJ. The fabricating steps involves forming a bottom write line, forming a MTJ on the bottom write, and forming a tape read line on the MTJ sequentially. In the circuit, the tape read line is either parallel to or vertical to the top write line.

Abstract: A method for fabricating an n-type carbon nanotube device, characterized in that thermal annealing and plasma-enhanced chemical vapor-phased deposition (PECVD) are employed to form a non-oxide gate layer on a carbon nanotube device. Moreover, the inherently p-type carbon nanotube can be used to fabricate an n-type carbon nanotube device with reliable device characteristics and high manufacturing compatibility.

Abstract: This specification discloses a manufacturing method of nanowire array. The method includes the steps of: providing a substrate; forming an insulating layer on the substrate; forming a metal catalyst layer on the insulating layer by spin on glass (SOG), the metal catalyst being Au, Ag, or Pt; forming a covering layer on the metal catalyst layer by SOG; patternizing the covering layer exposed out of the metal catalyst layer; etching the exposed metal catalyst layer to form a patternized metal catalyst layer; and forming a plurality of nanowires in the patternized metal catalyst layer.

Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.