Patents by Inventor Ming Ji

Ming Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11974482
    Abstract: A display substrate and related devices are provided. The display substrate includes a plurality of first sub-pixels, second sub-pixels and third sub-pixels. In a first direction, the first sub-pixels and the third sub-pixels are arranged alternately to form a plurality of first sub-pixel rows, the second sub-pixels form a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are arranged alternately in a second direction, connection lines of center points of two first sub-pixels and two third sub-pixels form a first virtual quadrilateral, the two first sub-pixels are located at two vertex angles of the first virtual quadrilateral which are opposite to each other, one second sub-pixel is located within the first virtual quadrilateral, and the first virtual quadrilateral includes two interior angles each being equal to 90° and two interior angles each being not equal to 90°.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 30, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qian Xu, Tong Niu, Yan Huang, Guomeng Zhang, Chang Luo, Jianpeng Wu, Peng Xu, Fengli Ji, Yi Zhang, Benlian Wang, Ming Hu
  • Patent number: 11967579
    Abstract: A method for forming a package structure is provided. The method includes etching a top surface of a substrate to form a cavity. The substrate includes thermal vias directly under a bottom surface of the cavity. The method also includes forming at least one first electronic device in the cavity of the substrate. The first electronic device is thermally coupled to the thermal vias. The method further includes forming an encapsulating material in the cavity, so that the encapsulating material extends along sidewalls of the first electronic device and covers a surface of the first electronic device opposite the bottom surface of the cavity. In Addition, the method includes forming an insulating layer having an RDL structure over the encapsulating material. The RDL structure is electrically connected to the first electronic device.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240125713
    Abstract: A method includes directing light at a first side of a semiconductor structure; detecting a first light intensity at a second side of the semiconductor structure, wherein the first light intensity corresponds to the light that penetrated the semiconductor structure from the first side to the second side; and comparing the first light intensity to a second light intensity, wherein the second light intensity corresponds to an expected intensity of light.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 18, 2024
    Inventors: Hao Chun Yang, Ming-Da Cheng, Pei-Wei Lee, Mirng-Ji Lii
  • Patent number: 11961944
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Ming-Da Cheng, Mirng-Ji Lii, Wen-Hsiung Lu, Cheng-Jen Lin, Chin-Wei Kang, Chang-Jung Hsueh
  • Publication number: 20240120735
    Abstract: An electrostatic discharge (ESD) circuit includes a first ESD detection circuit, a first discharging circuit and a first ESD assist circuit. The first ESD detection circuit is coupled between a first node having a first voltage and a second node having a second voltage. The first discharging circuit includes a first transistor. The first transistor has a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to the first ESD detection circuit by a third node. The first drain is coupled to the first node. The first source and the first body terminal are coupled together at the second node. The first ESD assist circuit is coupled between the second and third node, and configured to clamp a third voltage of the third node at the second voltage during an ESD event at the first or second node.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Lin HSU, Ming-Fu TSAI, Yu-Ti SU, Kuo-Ji CHEN
  • Patent number: 11942445
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a surface. The semiconductor device includes a conductive pad over a portion of the surface. The conductive pad has a curved top surface, and a width of the conductive pad increases toward the substrate. The semiconductor device includes a device over the conductive pad. The semiconductor device includes a solder layer between the device and the conductive pad. The solder layer covers the curved top surface of the conductive pad, and the conductive pad extends into the solder layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-En Yen, Chin-Wei Kang, Kai-Jun Zhan, Wen-Hsiung Lu, Cheng-Jen Lin, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240096647
    Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Mirng-Ji Lii, Chen-Shien Chen, Lung-Kai Mao, Ming-Da Cheng, Wen-Hsiung Lu
  • Patent number: 11935885
    Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Heng Chang, Kuo-Ji Chen, Ming-Hsiang Song
  • Publication number: 20240085717
    Abstract: Disclosed are a super-resolution imaging system (1, 41, 51), a super-resolution imaging method, a biological sample identification system (4, 61) and method, a nucleic acid sequencing imaging system (5) and method, and a nucleic acid identification system (6) and method. The super-resolution imaging system (1, 41, 51) includes an illumination system (A) and an imaging system (B). The illumination system (A) outputs excitation light to irradiate a biological sample to generate excited light, and the imaging system (B) collects and records the excited light to generate an excited light image. The illumination system (A) includes an excitation light source (10, 10a) and a structured light generation and modulation device (11, 11a). The excitation light source (10, 10a) outputs the excitation light, and the structured light generation and modulation device (11, 11a) modulates the excitation light into structured light to irradiate the biological sample to generate the excited light.
    Type: Application
    Filed: March 9, 2020
    Publication date: March 14, 2024
    Inventors: JIELEI NI, MING NI, FAN ZHOU, ZEYU SU, KE JI, DONG WEI, MENGZHE SHEN, YUANQING LIANG, MEI LI, XUN XU
  • Publication number: 20240088119
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 11926787
    Abstract: A well cementing method is described for improving cementing quality by controlling the hydration heat of cement slurry. By controlling the degree and/or rate of hydration heat release from cement slurry, the method improves the hydration heat release during formation of cement with curing of cement slurry, improves the binding quality between the cement and the interfaces, and in turn improves the cementing quality at the open hole section and/or the overlap section. The cementing method improves cementing quality of oil and gas wells and reduces the risk of annular pressure.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignees: PetroChina Company Limited, CNPC Engineering Technology R&D Company Limited
    Inventors: Shuoqiong Liu, Hua Zhang, Jianzhou Jin, Ming Xu, Yongjin Yu, Fengzhong Qi, Congfeng Qu, Hong Yue, Youcheng Zheng, Wei Li, Yong Ma, Youzhi Zheng, Zhao Huang, Jinping Yuan, Zhiwei Ding, Chongfeng Zhou, Chi Zhang, Zishuai Liu, Hongfei Ji, Yuchao Guo, Xiujian Xia, Yong Li, Jiyun Shen, Huiting Liu, Yusi Feng, Bin Lyu
  • Patent number: 11925343
    Abstract: A traction apparatus, comprising a clip portion (2) and a traction portion (1), the traction portion containing a closed traction structure (11); the closed traction structure being made from an elastic material; the clip portion comprising a main clip body (23, 25) and a clip arm (24, 26); the main clip body being capable of passing through a biopsy channel (4) of an endoscope (3), the clip arm being capable of clip the closed traction structure. Also disclosed is a traction ring used for the traction apparatus, the traction ring being a single closed traction structure or being formed by connecting several closed traction structures, the traction ring being made from an elastic material.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: March 12, 2024
    Assignees: MICRO-TECH (NANJING) CO., LTD., BEIJING FRIENDSHIP HOSPITAL, CAPITAL MEDICAL UNIVERSITY
    Inventors: Ming Ji, Jianjun Shuang, Zhenghua Shen, Changging Li, Derong Leng, Chunjun Liu, Jie Hu
  • Publication number: 20240075710
    Abstract: This application provides a housing, a terminal device, and a housing manufacturing method. The housing includes a magnesium-based metal matrix. A first aluminum-based metal layer and a second aluminum-based metal layer are respectively disposed on two sides of the magnesium-based metal matrix, a first transition layer is disposed between the magnesium-based metal matrix and the first aluminum-based metal layer, an appearance layer is disposed on a surface of a side that is of the first aluminum-based metal layer and that is away from the first transition layer, a second transition layer is disposed between the magnesium-based metal matrix and the second aluminum-based metal layer, and an electrical connection layer is disposed on a surface of a side that is of the second aluminum-based metal layer and that is away from the second transition layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Inventors: Dawei Ji, Ming Cai, Banghong Hu
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
  • Patent number: 11921782
    Abstract: The present disclosure provides a technical solution of multi-modal chatting, which may provide response to user query by using multi-modal response in the interaction between chatbot and human beings, so that the expressing ways and the expressed content by the chatbot could be richer by using such response in a multi-modal way.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 5, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Nan Duan, Lei Ji, Ming Zhou
  • Publication number: 20240047397
    Abstract: A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.
    Type: Application
    Filed: March 20, 2023
    Publication date: February 8, 2024
    Inventors: Bo-Yu CHIU, Pei-Wei LEE, Fu Wei LIU, Yun-Chung WU, Hao Chun YANG, Chin-Yu KU, Ming-Da CHENG, Ming-Ji LII
  • Publication number: 20240034619
    Abstract: A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.
    Type: Application
    Filed: January 9, 2023
    Publication date: February 1, 2024
    Inventors: Pei-Wei Lee, Fu Wei Liu, Szu-Hsien Lee, Yun-Chung Wu, Chin-Yu Ku, Ming-Da Cheng, Ming -Ji Lii
  • Patent number: 11864721
    Abstract: An endoscope end cap, including a sleeve member, protrusion elements, and a movable sleeve. The sleeve member is connected to the front end of an endoscope, the sleeve member, the protrusion elements, and the movable sleeve are connected in sequence, and the movable sleeve can move freely on the outer surface of the endoscope. When the endoscope is inserted for examination, the end cap is easy to enter and does not scratch the digestive tract since the end cap has a cylinder-like structure which is smooth and has no angularity; when the endoscope is being withdrawn, the movable sleeve moves distally and abuts against the sleeve member, so as to support the protrusion elements to enable the protrusion elements to dilate the inner wall of the intestine, improving the quality of single endoscope examination, and reducing discomfort of a patient, operation risk, and operation time.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 9, 2024
    Assignees: Micro-Tech (Nanjing) Co., Ltd., Beijing Friendship Hospital, Capital Medical University
    Inventors: Shutian Zhang, Ming Ji, Huihong Zhai, Jianjun Shuang, Jianyu Wei, Derong Leng, Changqing Li, Zhenghua Shen, Chunjun Liu
  • Patent number: 11821751
    Abstract: Aspects of the disclosure relate to validating map data using challenge questions. For instance, an attributes to be validated may be identified from the map data. At least one challenge question may be selected from a plurality of predetermined challenge questions based on the attribute. An image may be retrieved based on image information associated with the at least one challenge question. The image and the at least one challenge question may be provided for display. In response to the providing, operator input identifying an answer to the at least one challenge question may be received. This answer may be then used to validate the attribute.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: November 21, 2023
    Assignee: Waymo LLC
    Inventors: Michael Steven Montemerlo, Ming Ji, Peter Pawlowski
  • Publication number: 20230367306
    Abstract: A method and an apparatus for equipment anomaly detection are provided. In the method, multiple signals of an equipment during normal operation or appearance images of the equipment when an appearance is not damaged are acquired in advance by using a data acquisition device to train a machine learning model stored in a storage device. A real-time signal of the equipment during a current operation or a current image of the appearance of the equipment is acquired by using the data acquisition device, and input to the trained machine learning model to output a detection result indicating a current operation state of the equipment or a current state of the appearance of the equipment.
    Type: Application
    Filed: February 23, 2023
    Publication date: November 16, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Po-Han Chang, An-Chun Luo, Tien I Kao, Ming-Ji Dai, Yi-Jen Lin, Po-Huan Chou