Abstract: A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.

Abstract: A thermoelectric apparatus includes a first and a second assemblies, at least a first and a second heat conductors. The first assembly includes a first and a second substrates, and several first thermoelectric material sets disposed between the first and second substrates. The first substrate has at least a first through hole. The second assembly includes a third and a fourth substrates, and several second thermoelectric material sets disposed between the third and fourth substrates. The fourth substrate has at least a second through hole. Each of the first and second thermoelectric material sets has a p-type and an n-type thermoelectric element. The first and second heat conductors respectively penetrate the first and second through holes. Two ends of the first heat conductor respectively connect the second and fourth substrates, while two ends of the second heat conductor respectively connect the first and third substrates.

Abstract: A self-assembly apparatus for assembling a plurality of devices with a predetermined aspect ratio is provided. The self-assembly apparatus includes a guiding element, a vibration device, and a magnetic field inducing device. The guiding element has a mesh structure. The vibration device is coupled to the guiding element and configured to vibrate the guiding element. The magnetic field inducing device is disposed below the guiding element and configured to generate a time-varying magnetic field to rotate each of the devices. Through a collective effect of the vibration of the guiding element, the time-varying magnetic field, and the self-gravity of each of the devices, the devices are positioned on a plate between the guiding element and the magnetic field inducing device through the mesh structure.

Abstract: A self-assembly apparatus for assembling a plurality of devices with a predetermined aspect ratio is provided. The self-assembly apparatus includes a guiding element, a vibration device, and a magnetic field inducing device. The guiding element has a mesh structure. The vibration device is coupled to the guiding element and configured to vibrate the guiding element. The magnetic field inducing device is disposed below the guiding element and configured to generate a time-varying magnetic field to rotate each of the devices. Through a collective effect of the vibration of the guiding element, the time-varying magnetic field, and the self-gravity of each of the devices, the devices are positioned on a plate between the guiding element and the magnetic field inducing device through the mesh structure.

Abstract: A measurement method, a measurement apparatus, and a computer program product for measuring a thermoelectric module are provided. A temperature is provided to the thermoelectric module. A current is applied to the thermoelectric module to turn both sides of the thermoelectric module into a hot side and a cold side. The temperature of the hot side is higher than that of the cold side. A terminal voltage of the thermoelectric module, a hot side temperature of the hot side, and a cold side temperature of the cold side are measured at different time points. A thermoelectric relationship between the terminal voltages and differences between the hot side temperatures and the corresponding cold side temperatures is obtained according to the terminal voltages, the hot side temperatures, and the cold side temperatures. At least one first parameter of the thermoelectric module is estimated according to the thermoelectric relationship.

Abstract: A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. A chemical vapor deposition (CVD) diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer, wherein the first conductive pattern layer is enclosed by and spaced apart from the CVD diamond film. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.

Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Abstract: A light emitting apparatus comprising a substrate, a first functional chip and a first light emitting component is provided. The substrate, the first functional chip, and the first light emitting component have a plurality of first bumps. In addition, the first functional chip has a plurality of first vias. The first light emitting component and the first functional chip are stacked on the substrate. Hence, the first light emitting component is electrically connected to the first functional chip and the substrate by the first vias and the first bumps.

Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.

Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Abstract: A circuit board structure and a manufacturing method thereof are provided. The circuit board structure includes a composite substrate, a dielectric layer, and a circuit layer. The composite substrate includes a metal substrate doped with non-metal powders and a metal buffer layer. A surface of the metal buffer layer opposite to the other surface of the metal buffer layer in contact with the metal substrate is treated by a polishing process. The dielectric layer is formed on the polished surface of the metal buffer layer, and the circuit layer is formed on the dielectric layer. Alternatively, a barrier layer is interposed between the dielectric layer and the metal buffer layer for preventing a diffusion effect of the metal buffer layer.

Abstract: A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate. The first conductive trace is disposed on the conductive plug and on the substrate in the first area. The second conductive trace is disposed on the substrate in the second area. It is noted that the first conductive trace and the second conductive trace have the same material and the same shape. A measurement method of the above-mentioned test structure is also provided.

Abstract: A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. An ultrananocrystalline diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer and enclosed by the ultrananocrystalline diamond film, wherein the ultrananocrystalline diamond film and the first conductive pattern layer do not overlap with each other as viewed from a top-view perspective. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Abstract: An active solid heatsink device and fabricating method thereof is related to a high-effective solid cooling device, where heat generated by a heat source with a small area and a high heat-generating density diffuses to a whole substrate using a heat conduction characteristic of hot electrons of a thermionic (TI) structure, and the thermionic (TI) structure and a thermo-electric (TE) structure share the substrate where the heat diffuses to. Further, the shared substrate serves as a cold end of the TE structure, and the heat diffusing to the shared substrate is pumped to another substrate of the TE structure serving as a hot end of the TE structure.

Abstract: A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.