Patents by Inventor Ming Jie

Ming Jie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180204836
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Patent number: 9945022
    Abstract: A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: April 17, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Ming-Jie Cao, Li Guo, Ze-Dong Gao, Yao-Wei Wei
  • Patent number: 9917085
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Publication number: 20180003927
    Abstract: The present disclosure describes optical and optoelectronic assemblies that, in some cases, include screen-printed micro-spacers, as well as methods for manufacturing such assemblies and modules. For example, micro-spacers can be applied on a first optical element layer, and a second optical element layer can be provided on the first micro-spacers. By providing the second optical element layer on the first micro-spacers, the second optical element layer and the first optical element layer can be separated from one another by air or vacuum gaps each of which is laterally surrounded by a portion of the first micro-spacers.
    Type: Application
    Filed: June 23, 2017
    Publication date: January 4, 2018
    Applicant: Heptagon Micro Optics Pte. Ltd.
    Inventors: Guo Xiong Wu, Ming Jie Lee, Simon Gubser, Qichuan Yu, Joon Heng Tan
  • Publication number: 20180006192
    Abstract: The present disclosure describes wafer-level processes for fabricating optoelectronic device subassemblies that can be mounted, for example, to a circuit substrate, such as a flexible cable or printed circuit board, and integrated into optoelectronic modules that include one or more optical subassemblies stacked over the optoelectronic device subassembly. The optoelectronic device subassembly can be mounted onto the circuit substrate using solder reflow technology even if the optical subassemblies are composed of materials that are not reflow compatible.
    Type: Application
    Filed: June 23, 2017
    Publication date: January 4, 2018
    Applicant: Heptagon Micro Optics Pte. Ltd.
    Inventors: Hartmut Rudmann, Qichuan Yu, Simon Gubser, Bojan Tesanovic, Xu Yi, Eunice Ho Hui Ong, Hongyuan Liu, Ji Wang, Edmund Koon Tian Lua, Myo Paing, Jian Tang, Ming Jie Lee
  • Patent number: 9840769
    Abstract: An oxide semiconductor film includes indium (In), cerium (Ce), zinc (Zn) and oxygen (O) elements, and a molar ratio of the In, Ce, and Zn as In:Ce:Zn is in a range of 2:1:(0.5 to 2). A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CeZnxO5+x, wherein x=0.5˜2.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: December 12, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Ming-Jie Cao, Li Guo, Liang-Qi Ouyang, Ru-Jun Sun
  • Publication number: 20170345820
    Abstract: A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 30, 2017
    Inventors: Chih-Han Lin, Wen-Shuo Hsieh, Ming-Jie Huang, Ryan Chia-Jen Chen
  • Publication number: 20170343997
    Abstract: A method and apparatus for generating machining code of workpieces from a paper engineering drawing are provided. The method includes processing the paper engineering drawing to be a binary image; extracting dimension features and shape features of the workpieces from the binary image; and generating the machining codes of the workpieces based on the extracted dimension features and shape features of the workpieces. The machining codes indicate the dimension and shape of the workpieces, Machining codes of workpieces are generated from a paper engineering drawing directly without manual involvement.
    Type: Application
    Filed: December 1, 2014
    Publication date: November 30, 2017
    Applicant: Siemens Aktiengesellschaft
    Inventors: Shun Jie FAN, Ming JIE, Qian WANG
  • Patent number: 9828667
    Abstract: A method for making a SnO thin film includes steps of: providing a substrate and a tin oxide sputtering target; spacing the substrate and the tin oxide sputtering target from each other; and sputtering the SnO thin film on the substrate by using a magnetron sputtering method. The tin oxide sputtering target comprises uniformly mixed elemental Sn and SnO2. An atomic ratio of Sn atoms and O atoms in the tin oxide sputtering target satisfies 1:2<Sn:O?2:1.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: November 28, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Li Guo, Ming-Jie Cao, Liang-Qi Ouyang, Leng Zhang
  • Patent number: 9748367
    Abstract: A method for making a thin film transistor includes a step of forming a semiconducting layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer on an insulating substrate. A process of forming the semiconducting layer comprises a step of sputtering an oxide semiconductor film on a substrate by using a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: August 29, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Ming-Jie Cao, Li Guo, Ze-Dong Gao, Yao-Wei Wei
  • Patent number: 9732415
    Abstract: An oxide semiconductor film includes indium (In), cerium (Ce), zinc (Zn), doping metal element (M) and oxygen (O) elements, and a molar ratio of the In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 15, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Ming-Jie Cao, Li Guo, Leng Zhang, Yao-Wei Wei
  • Publication number: 20170047436
    Abstract: A method for making a thin film transistor includes a step of forming a semiconducting layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer on an insulating substrate. A process of forming the semiconducting layer comprises a step of sputtering an oxide semiconductor film on a substrate by using a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Application
    Filed: November 1, 2016
    Publication date: February 16, 2017
    Inventors: DA-MING ZHUANG, MING ZHAO, MING-JIE CAO, LI GUO, ZE-DONG GAO, YAO-WEI WEI
  • Publication number: 20170044655
    Abstract: A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Application
    Filed: October 31, 2016
    Publication date: February 16, 2017
    Inventors: DA-MING ZHUANG, MING ZHAO, MING-JIE CAO, LI GUO, ZE-DONG GAO, YAO-WEI WEI
  • Patent number: 9570627
    Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer, and a gate electrode. The drain electrode is spaced from the drain electrode. The semiconducting layer is electrically connected to the drain electrode and the source electrode. The semiconducting layer is an oxide semiconductor film comprising indium (In), cerium (Ce), zinc (Zn) and oxygen (O) elements, and a molar ratio of In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. The gate electrode is insulated from the semiconducting layer, the source electrode, and the drain electrode by the insulating layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: February 14, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Ming-Jie Cao, Li Guo, Ze-Dong Gao, Yao-Wei Wei
  • Publication number: 20170037506
    Abstract: An oxide semiconductor film includes indium (In), cerium (Ce), zinc (Zn) and oxygen (O) elements, and a molar ratio of the In, Ce, and Zn as In:Ce:Zn is in a range of 2:1:(0.5 to 2). A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CeZnxO5+x, wherein x=0.5˜2.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 9, 2017
    Inventors: DA-MING ZHUANG, MING ZHAO, MING-JIE CAO, LI GUO, LIANG-QI OUYANG, RU-JUN SUN
  • Publication number: 20170037505
    Abstract: An oxide semiconductor film includes indium (In), cerium (Ce), zinc (Zn), doping metal element (M) and oxygen (O) elements, and a molar ratio of the In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 9, 2017
    Inventors: DA-MING ZHUANG, MING ZHAO, MING-JIE CAO, LI GUO, LENG ZHANG, YAO-WEI WEI
  • Patent number: 9543210
    Abstract: A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions.
    Type: Grant
    Filed: September 5, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
  • Patent number: 9530640
    Abstract: An oxide semiconductor film includes indium (In), cerium (Ce), zinc (Zn) and oxygen (O) elements, and a molar ratio of the In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: December 27, 2016
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Da-Ming Zhuang, Ming Zhao, Ming-Jie Cao, Li Guo, Ze-Dong Gao, Yao-Wei Wei
  • Publication number: 20160329209
    Abstract: An oxide semiconductor film includes indium (In), cerium (Ce), zinc (Zn) and oxygen (0) elements, and a molar ratio of the In, Ce, and Zn as In:Ce:Zn is in a range of 2:(0.5 to 2):1. A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.
    Type: Application
    Filed: June 24, 2015
    Publication date: November 10, 2016
    Inventors: DA-MING ZHUANG, MING ZHAO, MING-JIE CAO, LI GUO, ZE-DONG GAO, YAO-WEI WEI
  • Patent number: D809703
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: February 6, 2018
    Assignee: ENERGY FOCUS, INC.
    Inventors: David Y. Lin, Ming Jie Tsai