Abstract: A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer.

Abstract: A phase change memory device is disclosed, including a substrate, a phase change layer over the substrate, a first electrode electrically connecting a first side of the phase change layer, a second electrode electrically connecting a second side of the phase change layer, wherein the phase change layer composes mainly of gallium (Ga), antimony (Sb) and tellurium (Te) and unavoidable impurities, having the composition range of GaxTeySbz, 5<x<40; 8?y<48; 42<z<80; and x+y+z=100.

Abstract: A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers.

Abstract: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.

Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.

Abstract: A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer.

Abstract: A phase change memory device is disclosed, including a substrate, a phase change layer over the substrate, a first electrode electrically connecting a first side of the phase change layer, a second electrode electrically connecting a second side of the phase change layer, wherein the phase change layer composes mainly of gallium (Ga), antimony (Sb) and tellurium (Te) and unavoidable impurities, having the composition range of GaxTeySbz, 5<x<40; 8?y<48; 42<x<80; and x+y+z=100.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate. A lamination structure is on the substrate along a first direction. The lamination structure comprises a plurality of conductive layers arranged from bottom to top and separated from each other, and each of the conductive layers has a channel region and an adjacent source/drain doped region along the first direction. A first gate structure is on a sidewall of the channel region of each conductive layer. The first gate structure comprises an inner first gate insulating layer and an outer first gate conductive layer.

Abstract: A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the composite layer. A phase-change material occupies at least one portion of the via hole. The composite layer comprises alternating layers or a mixture of the dielectric material and the low thermal conductivity material.

Abstract: Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a first electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer and the first electrode. A phase change material layer disposed in the second dielectric layer to electrically contact the first electrode. A third dielectric layer is disposed over the second dielectric layer. A second electrode is disposed in the third dielectric layer to electrically connect the phase change material layer and at least one gap disposed in the first dielectric layer or the second dielectric layer to thereby isolate portions of the phase change material layer and portions of the first or second dielectric layer adjacent thereto.

Abstract: A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase change memory structure comprises a cup-shaped heating electrode on the electrode layer. An insulating layer is on the cup-shaped heating electrode along a first direction covering a portion of the cup-shaped heating electrode. An electrode structure is on the cup-shaped heating electrode along a second direction covering a portion of the insulating layer and the cup-shaped heating electrode. A pair of double spacers is on a pair of sidewalls of the electrode structure covering a portion of the cup-shaped heating electrode, wherein the double spacer comprises a phase change material spacer and an insulating material spacer on a sidewall of the phase change material spacer.

Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Abstract: A method for fabricating trench MOS devices and termination structure simultaneously is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on the semiconductor substrate prepared. The method comprises following steps: firstly, forming a plurality of first trenches for forming the trench MOS devices in an active region, and a second trench for forming the termination structure. Thereafter, a thermal oxidation process to form a gate oxide on all areas is performed. Then, the first trenches and the second trench are refilled with a first conductive material. An etching back is carried out to remove excess first conductive material so as to form spacer in the second trench and to fill the first trenches only. Next, the gate oxide layer is removed. For IGBT or DMOS device, an extra thermal oxidation and an etching step are required to form inter-conductive oxide layer whereas for Schottky diode, these two steps are skipped.

Abstract: A design for a trench DMOS transistor having improved current carrying capability is presented. The principal improvement lies in the periodic replacement of the individual cells in the array with a protection cell of a different size. When this is done it becomes possible to significantly increase the density of cells per unit area. This results in a corresponding improvement in the amount of channel area available to the device and hence an increase in its current carrying capability.

Abstract: Unexpected results were obtained when Tl-1223 and Tl=-2223 superconductive materials were annealed at respectively pre-determined annealing temperatures. The optimum annealing temperatures for Tl-1223 and Tl-2223 superconductive materials are found to be 860.degree. C. and 820.degree. C., respectively. By incorporating the optimum annealing temperature and an optimum annealing envirenment, which is expressed in terms of oxygen partial pressure, into the manufacturing process, the present invention presents a method which can substantially increase the critical temperature of thallium based superconductive materials with greatly reduced annealing time and with improved reproducibility, and is thus superior to any method disclosed in the prior art.