Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

Abstract: A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.

Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

Abstract: A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface.

Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure.

Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract: A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.

Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract: A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member.

Abstract: A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.