Abstract: Systems and methods for use with a biological sample include a microscopy device, a diluent, a sample holder, and one or more of lyophilized cakes comprising artificial particles. The lyophilized cakes and the biological sample are mixed with the diluent in the sample holder to form a solution. The biological sample is imaged with the artificial particles as reference markers using the microscopy device. A settling time of the artificial particles is shorter than or equal to a settling time of the biological sample.

Abstract: A memory device including a memory array, a driver circuit, and a recover circuit is provided. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

Abstract: Methods for resource indication and a terminal device are provided in implementations of the disclosure. The method includes the following. A first terminal device transmits a shared resource set to a second terminal device through first signaling, where the shared resource set indicates transmission resources for sidelink (SL) communication.

Abstract: Embodiments of the present application provide a wireless communication method and a terminal device, in which cell reselection can be performed under a circumstance that the terminal device supports both LTE sidelink communication and NR sidelink communication. The wireless communication method includes: the terminal device determining a carrier priority order of multiple carriers used for cell reselection according to a carrier attribute, where the carrier attribute is for sidelink communication of at least two networks.

Abstract: The present disclosure provides a method for forming a multilayer wiring structure, which includes: forming a patterned copper-phosphorous alloy layer over a carrier by performing a plating operation, and forming a dielectric layer over the patterned copper-phosphorous alloy layer. The forming the patterned copper-phosphorous alloy layer includes providing a plating solution having a copper source and a phosphorous source.

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.

Abstract: A process gas is flowed from an input metal gas line that is electrically grounded to an output metal gas line via a connecting tube which is electrically insulating. Couplings between the metal gas lines and the connecting tube are sealed with gas couplings. Each gas coupling includes a sealing gasket, and a clamp compressing the sealing gasket between an end of the respective metal gas line and a corresponding end of the connecting tube. The process gas is delivered to a semiconductor processing tool via the output metal gas line. At least one operation is performed at the semiconductor processing tool that utilizes both the process gas delivered to the process tool via the output metal gas line and an electrical voltage of at least 2 kilovolts. The connecting tube may be sapphire. The sealing gaskets may be polytetrafluoroethylene (PTFE) sealing gaskets.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: Provided are a method and apparatus for wireless communication capable of meeting data transmission requirements. The method comprises: a first terminal determining, according to a first criterion, a target transmission power for a first physical sidelink channel; and the first terminal using the target transmission power to send the first physical sidelink channel to a second terminal.

Abstract: A graphics card including a circuit board module, a first heat dissipation fin, and a pair of fans is provided. The circuit board module includes a circuit board and a heat source. The circuit board has first to fourth sides surrounding the heat source. The first and second sides are opposite sides. The third and fourth sides are opposite sides. The first heat dissipation fin is in thermal contact with the heat source and has multiple channels communicating with the first to fourth sides. The fans disposed on the first and second sides respectively have first flow outlets facing the first heat dissipation fin and generate flows towards the first heat dissipation fin through the first flow outlets. The flows meet and squeeze in the channels to form turbulent flows and flow out of the graphics card through the third and fourth sides respectively. A computer host is also provided.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.

Abstract: Sensor-based privacy-event detection for a mounted electronic device is described. In aspects, a security system includes a head assembly removably and magnetically coupled to a mounting device having a magnet. The electronic device also includes a camera module and a sensor disposed within the housing. The sensor detects a magnetic field associated with the magnet when the head assembly is coupled to the mounting device. When a user detaches the head assembly from the mounting device (e.g., to recharge the electronic device), the sensor no longer detects the magnetic field and determines the occurrence of a privacy event, which is used to deactivate the camera module to prevent unintentional recordings during the privacy event.

Abstract: A wireless communication method and a terminal device are provided. The method includes: receiving, by a first terminal, a sidelink data channel and/or a sidelink reference signal transmitted by a second terminal; transmitting, by the first terminal, a first sidelink feedback channel to the second terminal, the first sidelink feedback channel carrying sidelink feedback information of the sidelink data channel and/or a measurement result of the sidelink reference signal, and the first sidelink feedback channel carrying information of more than one bit.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; a gate overlying the substrate; a channel layer separated from the gate by a dielectric and overlying the gate; source/drain regions on the channel layer, the gate extending between the source/drain regions; an insertion layer conforming to an upper surface of the channel layer and comprising a first material; and a passivation layer conforming to an upper surface of the insertion layer and comprising a second material different from the first material; where the passivation layer has a higher density than the insertion layer, such that the passivation layer mitigates the diffusion of environmental materials towards the channel layer, and where the insertion layer mitigates the diffusion of the second material from the passivation layer into the channel layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a second semiconductor layer on a first semiconductor layer. The first semiconductor layer and the second semiconductor layer have different energy bandgaps. The method further includes performing an etching process to form an opening exposing a first vertical sidewall of the first semiconductor layer and a second vertical sidewall of the second semiconductor layer. The method further includes forming an electrode structure in the opening to cover the first vertical sidewall and the second vertical sidewall.