Patents by Inventor Ming Lin
Ming Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250261047Abstract: A method of resource allocation and channel access in sidelink communication by a user equipment (UE) includes identifying, by the UE, one or more candidate reserved resources, wherein the UE is configured to share its channel occupancy time (COT) with the one or more candidate reserved resources, or the UE is configured to utilize a shared COT from the one or more candidate reserved resources.Type: ApplicationFiled: April 1, 2025Publication date: August 14, 2025Inventor: Huei-Ming LIN
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Patent number: 12389665Abstract: Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.Type: GrantFiled: January 11, 2024Date of Patent: August 12, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20250254663Abstract: Embodiments of the present application relate to a method, terminal device, and network device for transmitting sidelink data. The method includes that: a first terminal device receives sidelink transmission resource indication information and first uplink transmission resource indication information configured by a network device, where the sidelink transmission resource indication information is used for indicating a sidelink transmission resource, and the first uplink transmission resource indication information is used for indicating a first uplink transmission resource; the first terminal device transmits sidelink data to at least one second terminal device on the sidelink transmission resource; and the first terminal device transmits the first feedback information to the network device, where the first feedback information is used for indicating whether the sidelink data has been received correctly.Type: ApplicationFiled: April 22, 2025Publication date: August 7, 2025Inventors: Zhenshan ZHAO, Qianxi LU, Huei-Ming LIN
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Publication number: 20250254884Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.Type: ApplicationFiled: April 28, 2025Publication date: August 7, 2025Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Chi On Chui, Yu-Ming Lin
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Publication number: 20250254916Abstract: A method for manufacturing a semiconductor device includes: forming a channel including a semiconductor material; forming two intermediate conductive layers in contact with the channel and spaced apart from each other; and forming two conductive contacts respectively on the two intermediate conductive layers. Each of the intermediate conductive layers includes at least one stacking unit. The at least one stacking unit includes two first metal oxide layers spaced apart from each other and a second metal oxide layer disposed between the two first metal oxide layers and extending along a lengthwise line such that the two first metal oxide layers are opposite to each other relative to the lengthwise line. Each of the first metal oxide layers includes first metal atoms. The second metal oxide layer includes second metal atoms that are different from the first metal atoms.Type: ApplicationFiled: February 7, 2024Publication date: August 7, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Chieh HUANG, Huai-Ying HUANG, Yu-Chuan SHIH, Chun-Chieh LU, I-Che LEE, Yu-Ming LIN
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Publication number: 20250254662Abstract: A resource selection method for sidelink communication by a UE includes performing resource selection based on at least one of followings: selecting resources from consecutive RB sets for sidelink transmission, avoid selecting resources in a same slot from different RB sets for simultaneous transmission, selecting resources in consecutive time slots within a COT duration and within a same RB set, prioritizing or selecting resources for sidelink transmission within a self-initiated COT of the UE or a shared COT from another UE and within a same RB set as the self-initiated COT or the shared COT when a priority class of the sidelink transmission is equal to or larger than the self-initiated COT or the shared COT, performing CBR and/or a channel CR measurements per RB set and prioritizing/selecting a less loaded/congested RB set with lower measured CBR and/or CR values based on the CBR and/or the CR measurements, etc.Type: ApplicationFiled: April 22, 2025Publication date: August 7, 2025Inventor: Huei-Ming LIN
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Patent number: 12382640Abstract: An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).Type: GrantFiled: April 8, 2022Date of Patent: August 5, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Ling Lee, Wei-Gang Chiu, Yen-Chieh Huang, Han-Ting Tsai, Tsann Lin, Yu-Ming Lin, Chung-Te Lin
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Patent number: 12382709Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.Type: GrantFiled: January 5, 2024Date of Patent: August 5, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Chun-Yuan Chen, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 12381068Abstract: A radio frequency (RF) screen for a microwave powered ultraviolet (UV) lamp system is disclosed. In one example, a disclosed RF screen includes: a sheet comprising a conductive material; and a frame around edges of the sheet. The conductive material defines a predetermined mesh pattern of individual openings across substantially an operative area of the screen. Each of the individual openings has a triangular shape.Type: GrantFiled: May 17, 2024Date of Patent: August 5, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-chun Yang, Po-Wei Liang, Chao-Hung Wan, Yi-Ming Lin, Liu Che Kang
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Publication number: 20250248072Abstract: A semiconductor structure includes a base structure having a conductive feature therein, a transistor disposed above the base structure, a capacitor disposed on the transistor, and an interconnecting routing that interconnects the second electrode with the conductive feature. The transistor includes a gate electrode, a gate dielectric, a channel spaced apart from the gate electrode through the gate dielectric, and two contact structures connected to the channel and spaced apart from each other. Each of the two contact structures includes a main body, and a protection layer that includes a transition metal which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series. The capacitor includes a first electrode connected to one of the two contact structures of the transistor, a second electrode, and a dielectric interposed between the first electrode and the second electrode.Type: ApplicationFiled: January 29, 2024Publication date: July 31, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Che LEE, Wei-Gang CHIU, Huai-Ying HUANG, Yen-Chieh HUANG, Kai-Wen CHENG, Yu-Ming LIN
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Publication number: 20250246209Abstract: An electronic device includes a heat-dissipation bottom plate, a metal carrier disposed on the heat-dissipation bottom plate, a plurality of first thermally conductive pads assembled to the metal carrier, and a second thermally conductive pad that is assembled to the metal carrier. The metal carrier has an accommodating space configured to allow a hard disk drive (HDD) to be assembled therein. A memory module and at least one interface card are connected to the metal carrier through the first thermally conductive pads. The metal carrier or the HDD is connected to the heat-dissipation bottom plate through the second thermally conductive pad. The HDD, the memory module, and the at least one interface card are in cooperation with the first thermally conductive pads, the metal carrier, the second thermally conductive pad, and the heat-dissipation bottom plate for heat-dissipation.Type: ApplicationFiled: December 5, 2024Publication date: July 31, 2025Inventors: I-MING LIN, YI-SHU HSIEH, CHIA-HON JU, MING-JIE LEE
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Publication number: 20250248046Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer and a first alignment layer. The first alignment layer is disposed between the first electrode layer and the ferroelectric layer, and the ferroelectric layer and the first alignment layer have the same crystal lattice orientation. In some embodiments, a material of the first alignment layer has a band gap smaller than 50 meV.Type: ApplicationFiled: March 20, 2025Publication date: July 31, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 12376347Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.Type: GrantFiled: August 12, 2022Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chang Chiang, Yu-Chuan Shih, Chun-Chieh Lu, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
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Publication number: 20250239304Abstract: A memory device includes a memory cell having a first transistor, a second transistor, a first capacitor and a second capacitor coupled with each other into a data storage circuit configured to store a datum. The memory cell further has a third transistor and a fourth transistor coupled with each other into a comparison circuit configured to perform a comparison of the datum stored in the data storage circuit with a search input datum. The memory device further includes a back-end-of-line (BEOL) structure. The BEOL structure includes at least a part of the memory cell.Type: ApplicationFiled: May 10, 2024Publication date: July 24, 2025Inventors: Huai-Ying HUANG, Yu-Ming LIN
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Publication number: 20250241015Abstract: Oxide semiconductor ferroelectric field effect transistors (OS-FeFETs) and method of forming the same are provide. A device disclosed herein includes an electrode in a first dielectric layer, a ferroelectric layer over the electrode and the first dielectric layer, a high-k dielectric layer over the ferroelectric layer, an oxide semiconductor layer over the high-k dielectric layer, a second dielectric layer over the oxide semiconductor layer and the high-k dielectric layer, and a first contact feature and a second contact feature extending through the second dielectric layer to contact the oxide semiconductor layer.Type: ApplicationFiled: March 28, 2024Publication date: July 24, 2025Inventors: Chun-Chieh Lu, Yu-Chuan Shih, Yu-Ming Lin
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Publication number: 20250241064Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.Type: ApplicationFiled: April 9, 2025Publication date: July 24, 2025Inventors: Chun-Chieh LU, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia
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Publication number: 20250240973Abstract: A multiple-layer hydrogen barrier stack may be included between a non-volatile memory structure and conductive structures in an interconnect structure in a semiconductor device. The multiple-layer hydrogen barrier stack may minimize and/or prevent hydrogen diffusion into one or more layers of the non-volatile memory structure such as a metal-oxide channel of the non-volatile memory structure. The multiple-layer hydrogen barrier stack may include a hydrogen absorption layer and a hydrogen blocking layer on the hydrogen absorption layer. The hydrogen blocking layer blocks or resists diffusion of hydrogen through the conductive structures into the non-volatile memory structure. The hydrogen absorption layer may absorb any hydrogen atoms that might diffuse through the hydrogen blocking layer.Type: ApplicationFiled: January 18, 2024Publication date: July 24, 2025Inventors: Yen-Chieh HUANG, Huai-Ying HUANG, Wei-Gang CHIU, I-Chee LEE, Yu-Ming LIN
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Patent number: 12365770Abstract: A silica aerogel-containing polyester masterbatch includes a polyethylene terephthalate resin, a silica aerogel powder, and a dispersing agent. The silica aerogel powder is dispersed in the polyethylene terephthalate resin, and is present in an amount ranging from 5 wt % to 30 wt % based on 100 wt % of the silica aerogel-containing polyester masterbatch. The dispersing agent is dispersed in the polyethylene terephthalate resin, is selected from the group consisting of a paraffin oil, a silane compound, a wax including C28-C32 straight chain monoacids, and combinations thereof, and is present in an amount ranging from 0.1 wt % to 4.0 wt % based on 100 wt % of the silica aerogel-containing polyester masterbatch. A method for preparing the silica aerogel-containing polyester masterbatch, and a silica aerogel-containing polyester fiber made from the same are also disclosed.Type: GrantFiled: December 16, 2022Date of Patent: July 22, 2025Assignee: KCI MASTER INDUSTRIES CORP.Inventors: Yu-Shun Chen, Hsiao-Chi Tsai, Chun-Ping Cheng, Chien-Ming Lin, Hsu-Yeh Huang
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Patent number: 12369354Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.Type: GrantFiled: July 26, 2023Date of Patent: July 22, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wu-Wei Tsai, Chun-Chieh Lu, Hai-Ching Chen, Yu-Ming Lin, Sai-Hooi Yeong
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Patent number: 12368563Abstract: A data transmission method and related devices are provided. The method is applicable to a network device. The method includes the following. A physical downlink shared channel (PDSCH) is transmitted, and first configuration information is transmitted, where the PDSCH is used for carrying a first-type service, and the first configuration information is used for configuring a physical uplink control channel (PUCCH) resource. Uplink feedback information transmitted by a terminal device is received on the PUCCH resource, where the uplink feedback information indicates whether a service carried by the PDSCH is correctly received.Type: GrantFiled: July 6, 2022Date of Patent: July 22, 2025Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.Inventors: Zhenshan Zhao, Huei-Ming Lin