Abstract: Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line.

Abstract: A method for forming a semiconductor memory structure include forming a pillar structure. The pillar structure includes a first conductive layer, a second conductive layer and a data storage material layer between the first and second conducive layers. A sidewall of the first conductive layer, a sidewall of the data storage layer and a sidewall of the second conductive layer are exposed. An oxygen-containing plasma treatment is performed on the pillar structure to form hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer. An encapsulation layer is formed over the pillar structure and the dielectric layer. The encapsulation layer is in contact with the hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer.

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

Abstract: Provided are a method and apparatus for determining a time domain resource and a terminal device. The method includes: determining, by a terminal device, a first time slot set in a first period; and selecting, by the terminal device, a part of time slots from the first time slot set based on a first bitmap, the part of time slots forming the time domain resource of a resource pool.

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

Abstract: A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate dielectric layer is formed to wrap around semiconductor fin. A P-type work function layer is formed to wrap around the gate dielectric layer. An N-type work function layer is formed to wrap around the P-type work function layer. The N-type work function layer has a work function different from a work function of the P-type work function layer. The N-type work function layer is treated such that an upper portion of the N-type work function layer has a different composition than a lower portion of the N-type work function layer.

Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of finFETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A semiconductor structure includes a first dielectric layer, an electrode in the first dielectric layer, a second dielectric layer in the electrode, and a phase change material over the first dielectric layer, the electrode, and the second dielectric layer. According to some embodiments, an uppermost surface of the electrode is at least one of above an uppermost surface of the first dielectric layer, above an uppermost surface of the second dielectric layer, or above a lowermost surface of the phase change material.

Abstract: A method of fabricating a photonic device includes: forming a photonic device structure that includes a SOI substrate, which includes a bulk substrate layer, a buried oxide layer on the bulk substrate layer and an active semiconductor layer on the buried oxide layer; forming an electrically conducting layer in electrical contact of the buried oxide layer, and forming a BEOL structure on a surface of the active silicon layer.

Abstract: The treatment system provides a feature that may reduce cost of the electrochemical plating process by reusing the virgin makeup solution in the spent electrochemical plating bath. The treatment system provides a rotating filter shaft which receives the spent electrochemical plating bath and captures the additives and by-products created by the additives during the electrochemical plating process. To capture the additives and the by-products, the rotating filter shaft includes one or more types of membranes. Materials such as semi-permeable membrane are used to capture the used additives and by-products in the spent electrochemical plating bath. The treatment system may be equipped with an electrochemical sensor to monitor a level of additives in the filtered electrochemical plating bath.

Abstract: Provided is a laundry treating device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The isolation layer includes fluorine, and a first concentration of fluorine in the isolation layer increases toward a top surface of the isolation layer. The semiconductor device structure includes a gate stack over the isolation layer and wrapping around the fin portion.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The nozzle lips at the two sides of the slot die coating apparatus are extended to close the substrate to prevent to hit the obstacle of the substrate during coating. Also, the height for coating of the slot die coating apparatus is controllable to achieve the optimized coating.

Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first dielectric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.

Abstract: The invention provides a slot die coating apparatus and the coating method thereof. The flow path is divided into a first flow path and a second flow path by the shim group. The first flow path is utilized to coat from the middle portion of the coating nozzle and the second flow path is utilized to coat from the two sides of the coating nozzle. The height for coating of the slot die coating apparatus is adjustable, and the slurry may be exposed from the first flow path or the second flow path. Therefore, hitting the obstacle of the substrate can be avoided during coating to achieve the optimized coating.

Abstract: An access point receives restricted target wake time setup request information sent by a station. The restricted target wake time setup request information is used to request to set up a restricted target wake time. The access point sends restricted target wake time response information to the station. The restricted target wake time response information is used to respond to the restricted target wake time setup request information. The restricted target wake time setup request information or the restricted target wake time response information includes indication information of a first access category corresponding to low-latency traffic of the station. The station or the access point can independently and selectively configure the access category for the low-latency traffic.

Abstract: A field-effect transistor (FET), selectively switchable between first and second states, includes: source and drain regions and a channel region disposed therebetween; a gate arranged to selectively receive a bias voltage which switches the FET between the first and second states; a memory structure between the gate and the channel region, structure including a first portion which is anti-ferroelectric and a second portion which is ferroelectric, both portions being polarized in a first direction when the FET is in the first state; and a depolarization dielectric layer disposed proximate to the memory structure. When the FET is set to the first state, the depolarization dielectric layer destabilizes a polarization of the second portion of the memory structure while maintaining a polarization of the first portion.

Abstract: A display panel includes a first substrate and a shading structure. The shading structure is disposed on the first substrate. The shading structure includes a plurality of first parts and a second part. One of the plurality of first parts extends along a first direction. The second part protrudes from the one of the plurality of first part. Wherein the second part is separated from another one of the plurality of first parts adjacent to the one of the plurality of first parts, and the another one of the plurality of first parts extends along the first direction.