Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Abstract: Disclosed are a resource reselection method and a terminal device. The method includes: determining target selected slots and target sensing slots by a terminal device; obtaining a candidate resource set by performing resource exclusion on candidate resources in the target selected slots according to non-monitored slots and/or sensing result in the target sensing slots; and in a case where it is determined to perform reselection for a first resource that has been selected by the terminal device, selecting a second resource from the candidate resource set for replacement of the first resource.

Abstract: A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.

Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

Abstract: A pixel for an ambient light and/or color sensor includes a plurality of pinned photodiodes. The pixel also includes a floating diffusion region. A ratio of an active area of the plurality of pinned photodiodes to an area of the floating diffusion region is greater than 150.

Abstract: A micro light-emitting diode display device includes a substrate, a first planarization layer, a first light-emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate and has a first opening. The first opening has a first opening inner wall. The first light-emitting element is disposed on the substrate, in the first opening, and separated from the first opening inner wall. The second planarization layer is disposed on the substrate and between the first planarization layer and the first light-emitting element. The second planarization layer is in contact with the first light-emitting element.

Abstract: Provided by the implementations of the present application are a communication method and terminal, which may achieve reliability of system transmission by using a terminal-to-terminal mode to carry out communication. The method comprises: a first terminal device receiving a first sidelink transmission channel sent by a second terminal device, the first sidelink transmission channel being used to transmit a first message; in response to the first message, the first terminal device sending a second sidelink transmission channel to the second terminal device, the second sidelink transmission channel being used to transmit a second message, and the second message being a feedback message for the first message.

Abstract: A semiconductor manufacturing method is provided. The semiconductor manufacturing method includes the following steps. A first semiconductor element with a bonding film and a first stressing film is formed. The first bonding film and the first stressing film are formed on two opposite sides of the first semiconductor element. The first stressing film makes the first bonding film to have a first convex surface. A second semiconductor element with a second bonding film is formed. The second bonding film is formed on one side of the second semiconductor element. The first semiconductor element and the second semiconductor element are bonded by bonding the first bonding film and the second bonding film.

Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.

Abstract: A waveguide structure includes a substrate and a waveguide core coupled to the substrate and including a first material characterized by a first index of refraction and a first electro-optic coefficient. The waveguide structure also includes a first cladding layer at least partially surrounding the waveguide core and including a second material characterized by a second index of refraction less than the first index of refraction and a second electro-optic coefficient greater than the first electro-optic coefficient. The second cladding layer is coupled to the first cladding layer.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.

Abstract: A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.

Abstract: A quantitative evaluation method for integrity and damage evolution of a cement sheath in an oil-gas well is provided based on a fractal theory, an image processing technology, structural features and failure mechanisms of a casing-cement sheath-formation combination. The method uses correlations among fractal dimensions of casing-cement sheath interface morphology, cement sheath microscopic pore morphology, particle morphology of an initial blank group, and macroscopic mechanical properties including a radial cementing strength of the cement sheath interface, a tensile strength, and a compressive strength to quantitatively evaluate the integrity of the cement sheath of the blank group.