Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A method includes providing a structure having two fins extending from a substrate and an isolation structure adjacent to lower portions of the fins; forming a cladding layer over the isolation structure and over top and sidewalls of the fins; recessing the isolation structure using the cladding layer as an etch mask to expose the substrate; after the recessing of the isolation structure, depositing a seal layer over the substrate, the isolation structure, and the cladding layer; forming a sacrificial plug over the seal layer and between the two fins; and depositing a dielectric top cover over the sacrificial plug and laterally between the two fins.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.

Abstract: A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures.

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.