Patents by Inventor Ming-Ray Mao
Ming-Ray Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10290576Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.Type: GrantFiled: January 3, 2018Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20180145025Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.Type: ApplicationFiled: January 3, 2018Publication date: May 24, 2018Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9865534Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.Type: GrantFiled: June 13, 2016Date of Patent: January 9, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20160300794Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.Type: ApplicationFiled: June 13, 2016Publication date: October 13, 2016Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9373675Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.Type: GrantFiled: February 6, 2012Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Lin, Wen-Tsao Chen, Chih-Ho Tai, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9373536Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: GrantFiled: December 20, 2013Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9184154Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers.Type: GrantFiled: January 16, 2014Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chao Chen, Ming-Ray Mao, Shih-Hsien Yang, Kuan-Chi Tsai
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Publication number: 20140134801Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Inventors: Wen-Chao Chen, Ming-Ray Mao, Shih-Hsien Yang, Kuan-Chi Tsai
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Publication number: 20140106563Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: ApplicationFiled: December 20, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 8629559Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: GrantFiled: February 9, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20130207264Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20130200490Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Lin, Wen-Tsao Chen, Chih-Ho Tai, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20120190152Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers.Type: ApplicationFiled: January 25, 2011Publication date: July 26, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chao Chen, Ming-Ray Mao, Shih-Hsien Yang, Kuan-Chi Tsai
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Patent number: 6046475Abstract: A structure for manufacturing devices having inverse T-shaped well regions, which are formed on a substrate, comprises a first doped region and second doped region which have higher impurity concentrations and two third doped regions which have a lower impurity concentration. The first doped region formed on the substrate by a high-energy ion-implantation process is kept at a predetermined distance from the surface of the substrate. The second doped region extends from the surface of the substrate toward the downside to connect to the first doped region, such that two third doped regions are formed. The second doped region is formed by an ion-implantation process through an opening of a mask. Furthermore, a gate is formed above the second doped region, and source and drain regions are formed on the substrate. Therefore, a device having an inverse T-shaped well region is completely fabricated.Type: GrantFiled: May 29, 1997Date of Patent: April 4, 2000Assignee: National Science CouncilInventors: Kow-Ming Chang, Ji-yi Yang, Ming-Ray Mao