Methods for Fabricating Integrated Passive Devices on Glass Substrates
A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers.
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Integrated passive devices are used in mixed-signal circuits, analog circuits, radio frequency (RF) circuits, dynamic random access memories (DRAMs), embedded DRAM circuits, logic operation circuits, and the like. Integrated passive devices include capacitors, inductors, transformers, resistors, and the like.
The formation of the integrated passive devices may be similar to the processes for forming active devices, wherein starting from a silicon substrate, dielectric layers are formed layer by layer, and metal lines and vias are formed in the dielectric layers. Passive devices are also formed in the dielectric layers.
The conventional integrated passive devices often suffer from low performance that cannot meet the requirement of RF circuits. For example, the Q-factors of the capacitors in the conventional integrated passive devices are low, and the bandwidths of the inductors are narrow. The low performance of the integrated passive devices may be caused by Eddy currents in the respective substrates.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
A novel method for forming a device (such as a die) comprising integrated passive devices therein is provided. The intermediate stages of manufacturing an embodiment are illustrated. The variations of the embodiment are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Dielectric layer 14 is formed over, and may contact, substrate 10. Dielectric layer 14 may be formed of silicon nitride, for example. The thickness of dielectric layer 14 may be between about 2 kÅ and about 10 kÅ, for example. It is realized, however, that the dimensions recited throughout the description are merely examples, and may be changed in alternative embodiments. A plurality of dielectric layers 18 are formed over dielectric layer 14. Dielectric layers 18 may be formed of oxides such as Un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials such as low-k carbon containing oxides, or the like. The low-k dielectric materials may have k values lower than 3.8, although the dielectric materials of dielectric layers 18 may also be close to 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5.
Etch stop layers 20 are also formed between dielectric layers 18. In an embodiment, etch stop layers 20 are formed of silicon nitride, although other dielectric materials may be used, providing etch stop layers 20 and dielectric layers 18 have a high etching selectivity.
Metal lines 26 and vias 28 are formed in dielectric layer 18. Metal lines 26 and vias 28 may be formed of substantially pure copper (for example, with a weight percentage of copper being greater than about 90 percent, or greater than about 95 percent) or copper alloys, and may be formed using single and/or dual damascene processes. Metal lines 26 and vias 28 may also be formed of, or may be substantially free from, aluminum. Throughout the description, the term “metal layer” is used to refer to the collection of the metal lines in the same layer. Accordingly, the structure as shown in
In addition to metal lines 26 and vias 28, integrated passive devices 30 (denoted as 30A and 30B) such as capacitors, inductors, resistors, transformers, baluns, and the like, are also formed in dielectric layers 18. For example, capacitor 30A is schematically illustrated in the form of a Metal-Insulator-Metal (MIM) capacitor, although the capacitors may be other types of capacitors such as Metal-Oxide-Metal (MOM) capacitors. Furthermore, inductor 30B is schematically illustrated, wherein the illustrated portion of inductor 30B represents a cross-sectional view of a portion of the inductor. Integrated passive devices 30 may be formed using a single metal layer or stacked metal layers.
Over top metal layer Mtop, etch stop layer 40, thick oxide layer 42, and thick nitride layer 44 are formed. In an exemplary embodiment, oxide layer 42 has a thickness between about 100 Å and about 10 μm, and nitride layer 44 has a thickness between about 100 Å and about 10 μm. Nitride layer 44 and oxide layer 42 in combination are also referred to as being passivation layer 42/44.
Next, refer to
As shown in
Referring to
After the formation of metal bumps 62, the structure as shown in
Next, as shown in
In subsequent process steps, as shown in
In the embodiments, as shown in
In accordance with embodiments, a method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers. The plurality of dielectric layers may be sawed along with the dielectric substrate.
In accordance with other embodiments, a method includes forming a dielectric layer over a semiconductor substrate; forming a plurality of dielectric layers over the dielectric layer; and forming integrated passive devices in the plurality of dielectric layers. A passivation layer is then formed over the plurality of dielectric layers. A carrier wafer is bonded onto the passivation layer. The semiconductor substrate is removed and the dielectric layer is exposed. A glass substrate is bonded onto the dielectric layer. The carrier wafer is then removed from the passivation layer and the plurality of dielectric layers.
In accordance with yet other embodiments, a method includes forming a dielectric layer over a semiconductor substrate; forming a plurality of dielectric layers over the dielectric layer, with integrated passive devices formed in the plurality of dielectric layers; and forming a passivation layer over the plurality of dielectric layers. A glass substrate is bonded onto the passivation layer. The semiconductor substrate is removed. Metal bumps are then formed, wherein the metal bumps and the glass substrate are on located opposite sides of the plurality of dielectric layers.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims
1. A method comprising:
- forming a plurality of dielectric layers over a semiconductor substrate;
- forming integrated passive devices in the plurality of dielectric layers;
- removing the semiconductor substrate from the plurality of dielectric layers; and
- bonding a dielectric substrate onto the plurality of dielectric layers.
2. The method of claim 1, wherein the dielectric substrate and the semiconductor substrate are on a same side of the plurality of dielectric layers.
3. The method of claim 2 further comprising:
- bonding a carrier wafer on the plurality of dielectric layers, wherein the carrier wafer and the semiconductor substrate are on opposite sides of the plurality of dielectric layers;
- after the step of bonding the carrier wafer, performing the step of removing the semiconductor substrate;
- performing the step of bonding the dielectric substrate, with the dielectric substrate and the carrier wafer being on opposite sides of the plurality of dielectric layers; and
- after the step of bonding the dielectric substrate, removing the carrier wafer.
4. The method of claim 2 further comprising forming metal bumps, wherein the metal bumps and the dielectric substrate are on opposite sides of the plurality of dielectric layers.
5. The method of claim 1, wherein the dielectric substrate and the semiconductor substrate are on opposite sides of the plurality of dielectric layers.
6. The method of claim 5, wherein the step of bonding the dielectric substrate is performed before the step of removing the semiconductor substrate.
7. The method of claim 5 further comprising, after the step of removing the semiconductor substrate, forming metal bumps, wherein the metal bumps and the dielectric substrate are on opposite sides of the plurality of dielectric layers.
8. The method of claim 1, wherein the dielectric substrate comprises a glass substrate.
9. The method of claim 1 further comprising sawing the dielectric substrate and the plurality of dielectric layers into a plurality of dies, with each of the plurality of dies comprising a piece of the dielectric substrate.
10. A method comprising:
- forming a dielectric layer over a semiconductor substrate;
- forming a plurality of dielectric layers over the dielectric layer;
- forming integrated passive devices in the plurality of dielectric layers;
- forming a first passivation layer over the plurality of dielectric layers;
- bonding a carrier wafer onto the first passivation layer;
- removing the semiconductor substrate to expose the dielectric layer;
- bonding a glass substrate onto the dielectric layer; and
- removing the carrier wafer from the first passivation layer and the plurality of dielectric layers.
11. The method of claim 10, wherein after the step of removing the carrier wafer, the first passivation layer is exposed, and wherein the method further comprises:
- forming metal vias in the first passivation layer; and
- forming metal bumps over the first passivation layer, wherein the metal bumps are electrically coupled to the integrated passive devices through the metal vias.
12. The method of claim 11 further comprising:
- forming aluminum-containing pads over the first passivation layer, wherein the aluminum-containing pads are electrically coupled to the integrated passive devices through the metal vias;
- forming a second passivation layer over the aluminum-containing pads;
- forming under-bump metallurgies (UBMs) extending into openings in the second passivation layer and electrically coupled to the aluminum-containing pads; and
- performing the step of forming the metal bumps.
13. The method of claim 10, wherein the integrated passive devices are selected from the group consisting essentially of capacitors, inductors, and combinations thereof.
14. The method of claim 10 further comprising sawing the glass substrate and the plurality of dielectric layers into a plurality of dies, with each of the plurality of dies comprising a piece of the glass substrate.
15. The method of claim 10, wherein the semiconductor substrate is a silicon substrate.
16. A method comprising:
- forming a dielectric layer over a semiconductor substrate;
- forming a plurality of dielectric layers over the dielectric layer, with integrated passive devices formed in the plurality of dielectric layers;
- forming a first passivation layer over the plurality of dielectric layers;
- bonding a glass substrate onto the first passivation layer;
- removing the semiconductor substrate; and
- forming metal bumps, wherein the metal bumps and the glass substrate are on opposite sides of the plurality of dielectric layers.
17. The method of claim 16 further comprising:
- before the step of forming the metal bumps, forming aluminum-containing pads on an opposite side of the plurality of dielectric layers than the glass substrate, wherein the aluminum-containing pads are electrically coupled to the integrated passive devices through metal vias in the dielectric layer;
- forming a second passivation layer contacting the aluminum-containing pads;
- forming under-bump metallurgies (UBMs) extending into openings in the second passivation layer and electrically coupled to the aluminum-containing pads; and
- performing the step of forming the metal bumps.
18. The method of claim 16, wherein the integrated passive devices are selected from the group consisting essentially of capacitors, inductors, and combinations thereof.
19. The method of claim 16 further comprising sawing the glass substrate and the plurality of dielectric layers into a plurality of dies, with each of the plurality of dies comprising a piece of the glass substrate and a piece of the plurality of dielectric layers.
20. The method of claim 16, wherein the semiconductor substrate is a silicon substrate.
Type: Application
Filed: Jan 25, 2011
Publication Date: Jul 26, 2012
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Wen-Chao Chen (Chiayi City), Ming-Ray Mao (Tainan City), Shih-Hsien Yang (Zhubei City), Kuan-Chi Tsai (Kaohsiung City)
Application Number: 13/013,393
International Classification: H01L 21/02 (20060101);