Abstract: A circuit carrier is provided. The circuit carrier includes a substrate, a patterned circuit layer, and a solder mask layer. The patterned circuit layer is deposed on a surface of the substrate and has two passive component electrode pads. The solder mask layer covers the surface of the substrate, and includes a first solder mask opening, a second solder mask opening, and a third solder mask opening. The first solder mask opening and the second solder mask opening expose the passive component electrode pads respectively. The third solder mask opening along its length direction is divided into a central area and two extension areas. The central area is between the first and the second solder mask openings. The extension areas are extending from the central area along the length direction to two sides, respectively. The width of the central area is smaller than the width of one the extension areas.

Abstract: A circuit carrier is provided. The circuit carrier comprises a substrate, a patterned circuit layer, and a solder mask layer. The patterned circuit layer is deposed on a surface of the substrate and has two passive component electrode pads. The solder mask layer covers the surface of the substrate, and includes a first solder mask opening, a second solder mask opening, and a third solder mask opening. The first solder mask opening and the second solder mask opening expose the passive component electrode pads respectively. The third solder mask opening along its length direction is divided into a central area and two extension areas. The central area is between the first and the second solder mask openings. The extension areas are extending from the central area along the length direction to two sides, respectively. The width of the central area is smaller than the width of one the extension areas.

Abstract: An automatic integrated circuit testing system, device and method using an integrative computer. The system includes a machine frame having at least one testing computer for holding and testing the integrated circuit. The machine frame also has at least one automatic plugging/unplugging machine for engaging the integrated circuits with the computer system and removing the integrated circuits after testing has been completed. The machine frame further includes at least one controller device electrically connected to the testing computer and the automatic plugging/unplugging machine for controlling the movements of the automatic plugging/unplugging machine and the testing computer. The testing computer and the integrated circuit together form an integrative computer system capable of executing various general application programs and special testing programs for integrative testing and analysis.

Abstract: A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer.

Abstract: An automatic computer-system-level IC testing system comprises a testing computer, an IC mounting/retrieving mechanism, a temperature regulator, and a control unit. The testing computer connects and tests the IC that is arranged in the testing computer and retrieved there from via the IC mounting/retrieving mechanism. The temperature regulator regulates the testing temperature the IC being tested. The control unit is connected to the testing computer and the IC mounting/retrieving mechanism to supervise the testing process. Once the IC to be tested in connected therein, the testing computer forms a complete computer system through the operation of which the testing is performed.

Abstract: An automatic system-level test apparatus that includes a testing computer and at least one image sensor. The testing computer is used to carry and test an integrated circuit. The testing computer together with the integrated circuit incorporated therein forms a system-completed computer capable of conducting a system-level test. The testing computer includes at least one output device for outputting test images while running a pre-determined test program. An image sensor captures the images produced by the output device. The captured image is compared with an original image stored inside an image database to determine if a difference between the captured image and the stored image.

Abstract: A control method for an automatic integrated circuit full testing system. A control device is utilized to control the testing process of the automatic integrated circuit full testing system. The steps for controlling the control device include driving an automatic transport device to fetch test integrated circuits from an integrated circuit supply rack to various testing computer stations. An automatic plug/unplug tool is driven so that each integrated circuit is plugged into the connector of a corresponding testing computer. All the testing computers are triggered to carry out respective preset testing programs. An image sensor is driven to monitor the an output image of the testing computers so that any abnormality in the integrated circuits can be determined. Thereafter, the automatic plug/unplug tool is driven to unload the tested integrated circuit from the testing computer.

Abstract: An automatic integrated circuit testing system, device and method using an integrative computer. The system includes a machine frame having at least one testing computer for holding and testing the integrated circuit. The machine frame also has at least one automatic plugging/unplugging machine for engaging the integrated circuits with the computer system and removing the integrated circuits after testing has been completed. The machine frame further includes at least one controller device electrically connected to the testing computer and the automatic plugging/unplugging machine for controlling the movements of the automatic plugging/unplugging machine and the testing computer. The testing computer and the integrated circuit together form an integrative computer system capable of executing various general application programs and special testing programs for integrative testing and analysis.

Abstract: An IC tray for carrying IC packages that prevents incorrect placement of IC packages is provided. The tray includes a number of IC cavities used to accommodate the IC packages, with each of the IC packages having been provided with the second direction indicator that corresponds to the first direction indicator that each of the IC cavity has, preventing the IC packages from being placed into the IC tray in wrong directions. The IC tray prevents the users or operators from placing the IC packages into it in wrong directions, therefore effectively improves the convenience and yield rate in the subsequent manufacturing processes.

Abstract: An IC tray for carrying IC packages that prevents incorrect placement of IC packages is provided. The tray includes a number of IC cavities used to accommodate the IC packages, with each of the IC packages having been provided with the second direction indicator that corresponds to the first direction indicator that each of the IC cavity has, preventing the IC packages from being placed into the IC tray in wrong directions. The IC tray prevents the users or operators from placing the IC packages into it in wrong directions, therefore effectively improves the convenience and yield rate in the subsequent manufacturing processes.

Abstract: A method for fabricating a trench isolation is disclosed. First, a first insulated layer having a void is formed within the trench of the semiconductor. Next, the upper portion of said first insulated layer is etched to remove the void of said first insulated layer. Then, a second insulated layer having a void is formed over the first insulated layer. Next, the upper portion of said second insulated layer is etched to remove the void of said second insulated layer, thereby forming a trench isolation including the remainder of said first and second insulated layers.