Patents by Inventor Ming Sang Kwan
Ming Sang Kwan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7626869Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.Type: GrantFiled: May 7, 2007Date of Patent: December 1, 2009Assignee: Spansion LLCInventors: Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene G. Hamilton, Ashot Melik-Martirosian, Gulzar Kathawala, Ming Sang Kwan, Mark Randolph, Timothy Thurgate
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Patent number: 7599228Abstract: A memory device is provided including circuitry for correcting an over-erased memory cell in the memory device. The memory device may include a substrate. A control gate and a floating gate may be formed over the substrate. The memory device may include a source region and a drain region. A first resistive element may be coupled between the source region and the control gate.Type: GrantFiled: November 1, 2004Date of Patent: October 6, 2009Assignee: Spansion L.L.C.Inventors: Qiang Lu, Kuo-Tung Chang, Kazuhiro Mizutani, Sung-Chul Lee, Sheung-Hee Park, Ming-Sang Kwan
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Patent number: 7561471Abstract: Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.Type: GrantFiled: March 16, 2007Date of Patent: July 14, 2009Assignee: Spansion LLCInventors: Sheung-Hee Park, Xuguang Wang, Wing Leung, Ming-Sang Kwan, Yi He, Edward Franklin Runnion
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Patent number: 7553727Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.Type: GrantFiled: March 16, 2007Date of Patent: June 30, 2009Assignee: Spansion LLCInventors: Ming-Sang Kwan, Bradley Marc Davis, Jean Yee-Mei Yang, Zhizheng Liu, Yi He
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Publication number: 20080279014Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Applicant: SPANSION LLCInventors: Xuguang Wang, Yi He, Zhizheng Liu, Sung-Yong Chung, Darlene G. Hamilton, Ashot Melik-Martirosian, Gulzar Kathawala, Ming Sang Kwan, Mark Randolph, Timothy Thurgate
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Publication number: 20080153269Abstract: The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
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Publication number: 20080153223Abstract: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back endType: ApplicationFiled: March 16, 2007Publication date: June 26, 2008Inventors: Zhizheng Liu, Shankar Sinha, Timothy Thurgate, Ming-Sang Kwan
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Publication number: 20080150006Abstract: The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.Type: ApplicationFiled: March 16, 2007Publication date: June 26, 2008Inventors: Ming-Sang Kwan, Bradley Marc Davis, Jean Yee-Mei Yang, Zhizheng Liu, Yi He
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Publication number: 20080151644Abstract: Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.Type: ApplicationFiled: March 16, 2007Publication date: June 26, 2008Inventors: Sheung-Hee Park, Xuguang Wang, Wing Leung, Ming-Sang Kwan, Yi He, Edward Franklin Runnion
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Publication number: 20080153274Abstract: A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: Timothy Thurgate, Yi He, Ming-Sang Kwan, Zhizheng Liu, Xuguang Wang
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Publication number: 20080150007Abstract: The present invention facilitates memory devices and operation of dual bit and single bit memory devices by providing systems and methods that employ a salicide block to vary and equalize the resistance of a memory array during fabrication. The present invention includes utilizing a common charge dissipation region to mitigate charge-loss by providing protection against charging up of the various lines as a result of further plasma etching processes. The salicide block equalizes the charge dissipation in the memory array by providing each wordline path with a varied amount of resistance in addition to the total path resistance. Because the charge protection provided to each wordline otherwise varies depending on the resistance path to a common discharge element, a salicide block for resistance equalization provides greater reliability and predictability during processing. Other such shapes conducive for any desired resistance path fall within the scope of the invention.Type: ApplicationFiled: May 14, 2007Publication date: June 26, 2008Inventors: Michael Brennan, Yi He, Mark Randolph, Ming-Sang Kwan
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Publication number: 20080135902Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Inventors: Shankar Sinha, Yi He, Zhizheng Liu, Ming-Sang Kwan
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Publication number: 20080037330Abstract: A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.Type: ApplicationFiled: August 2, 2006Publication date: February 14, 2008Inventors: Sheung-Hee Park, Gwyn Jones, Wing Leung, Edward Franklin Runnion, Ming-Sang Kwan, Xuguang Wang, Yi He
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Patent number: 7319615Abstract: A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.Type: GrantFiled: August 2, 2006Date of Patent: January 15, 2008Assignee: Spansion LLCInventors: Sheung-Hee Park, Gwyn Jones, Wing Leung, Edward Franklin Runnion, Ming-Sang Kwan, Xuguang Wang, Yi He
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Patent number: 7154141Abstract: A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.Type: GrantFiled: February 2, 2001Date of Patent: December 26, 2006Assignee: Hyundai Electronics AmericaInventors: Hsingya Arthur Wang, Yuan Tang, Haike Dong, Ming Sang Kwan, Peter Rabkin
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Patent number: 7079424Abstract: A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.Type: GrantFiled: September 22, 2004Date of Patent: July 18, 2006Assignee: Spansion L.L.C.Inventors: Sungchul Lee, Sheunghee Park, Yue-Song He, Ming Sang Kwan
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Patent number: 6894925Abstract: A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.Type: GrantFiled: January 14, 2003Date of Patent: May 17, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Sheunghee Park, Sameer S. Haddad, Chi Chang, Richard M. Fastow, Ming Sang Kwan, Zhigang Wang
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Patent number: 6747900Abstract: A memory circuit for programming a target cell is disclosed. According to one embodiment, the memory circuit comprises the target cell having a drain terminal connected to a bit line. A drain voltage is coupled to the bit line and supplies a voltage greater than a ground voltage, while a gate voltage is coupled to a gate terminal of the target cell and supplies a voltage greater the ground voltage. A source voltage is coupled to a source terminal of the target cell and supplies a voltage less than the ground voltage, and a substrate voltage is coupled to a substrate of the target cell and supplies a voltage less than the ground voltage.Type: GrantFiled: January 21, 2003Date of Patent: June 8, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Sheunghee Park, Ming Sang Kwan
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Publication number: 20020105036Abstract: A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.Type: ApplicationFiled: February 2, 2001Publication date: August 8, 2002Inventors: Hsingya Arthur Wang, Yuan Tang, Haike Dong, Ming Sang Kwan, Peter Rabkin
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Publication number: 20020048192Abstract: A structure for a flash memory cell is described in which a triple well is formed with the memory cell residing in a P-well, which in turn is deposed in an N-well in a P-type substrate. The structure provides the ability to operate such memories with considerably lower operating potentials than prior art devices. A process for fabricating the flash memory cell is also described.Type: ApplicationFiled: October 12, 2001Publication date: April 25, 2002Inventors: Hsingya Arthur Wang, Jein-Chen Young, Ming-Sang Kwan