Patents by Inventor Ming-Shi Liou
Ming-Shi Liou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10083728Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.Type: GrantFiled: July 6, 2014Date of Patent: September 25, 2018Assignee: MediaTek Inc.Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Pin Chen
-
Patent number: 9557764Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.Type: GrantFiled: December 28, 2015Date of Patent: January 31, 2017Assignee: MEDIATEK INC.Inventors: Chen-Feng Chiang, Kai-Hsin Chen, Ming-Shi Liou, Chih-Tsung Yao
-
Publication number: 20160132071Abstract: A clock tree circuit Including a first clock source, generating a first signal, and a first tree circuit. The first clock tree circuit includes a first driving stage for receiving the first signal, a second driving stage, connected to the first driving stage, a third driving stage, connected to the second driving stage, and a metal connection element, coupled between different nodes of the third driving stage and configured as a short-circuited element.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventors: Chen-Feng CHIANG, Kai-Hsin CHEN, Ming-Shi LIOU, Chih-Tsung YAO
-
Patent number: 9256245Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.Type: GrantFiled: January 22, 2015Date of Patent: February 9, 2016Assignee: MEDIATEK INC.Inventors: Chen-Feng Chiang, Kai-Hsin Chen, Ming-Shi Liou, Chih-Tsung Yao
-
Publication number: 20150286243Abstract: A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.Type: ApplicationFiled: January 22, 2015Publication date: October 8, 2015Inventors: Chen-Feng CHIANG, Kai-Hsin CHEN, Ming-Shi LIOU, Chih-Tsung YAO
-
Publication number: 20150074346Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.Type: ApplicationFiled: July 6, 2014Publication date: March 12, 2015Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Pin Chen
-
Patent number: 8952718Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.Type: GrantFiled: August 10, 2012Date of Patent: February 10, 2015Assignee: Mediatek Inc.Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Ping Chen
-
Publication number: 20140321473Abstract: An active output buffer controller is used for controlling a packet data output of a main buffer in a network device. The active output buffer controller has a credit evaluation circuit and a control logic. The credit evaluation circuit estimates a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device. The control logic compares the credit value with a first predetermined threshold value to generate a comparison result, and controls the packet data output of the main buffer according to at least the comparison result.Type: ApplicationFiled: March 31, 2014Publication date: October 30, 2014Applicant: MEDIATEK INC.Inventors: Yu-Hsun Chen, Yi-Hsin Yu, Ming-Shi Liou, Ming Zhang
-
Publication number: 20130113516Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.Type: ApplicationFiled: August 10, 2012Publication date: May 9, 2013Applicant: MEDIATEK INC.Inventors: Yan-Bin LUO, Sheng-Ming CHANG, Bo-Wei HSIEH, Ming-Shi LIOU, Chih-Chien HUNG, Shang-Ping CHEN
-
Publication number: 20120272013Abstract: A data access system includes a memory controller, a first memory rank, a second memory rank, a first chip select bus coupled between the memory controller and the first memory rank, a second chip select bus coupled between the memory controller and the second memory rank, a group of shared buses shared by the first and second memory ranks and coupled between the memory controller and each of the first and second memory ranks, a first group of dedicated buses dedicated to the first memory rank and coupled between the memory controller and the first memory rank, and a second group of dedicated buses dedicated to the second memory rank and coupled between the memory controller and the second memory rank.Type: ApplicationFiled: April 25, 2011Publication date: October 25, 2012Inventor: Ming-Shi Liou
-
Patent number: 7779215Abstract: A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.Type: GrantFiled: March 4, 2005Date of Patent: August 17, 2010Assignee: VIA Technologies Inc.Inventors: Ming-Shi Liou, Bowei Hsieh, Jiin Lai
-
Patent number: 7610454Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.Type: GrantFiled: February 2, 2007Date of Patent: October 27, 2009Assignee: VIA Technologies Inc.Inventor: Ming-Shi Liou
-
Patent number: 7573759Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.Type: GrantFiled: September 28, 2006Date of Patent: August 11, 2009Assignee: Via Technologies, Inc.Inventors: Bo-Wei Hsieh, Ming-Shi Liou, Weber Chuang, Chi Chang
-
Patent number: 7552292Abstract: A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the memory space to different memory ranks. First, the distributive rule of the data is defined. Next, the data is distributed to the memory ranks that the data belongs to according to the rule. Then, the data is physically accessed in one of the memory ranks.Type: GrantFiled: March 17, 2005Date of Patent: June 23, 2009Assignee: Via Technologies, Inc.Inventors: Bo-Wei Hsieh, Ming-Shi Liou
-
Patent number: 7444535Abstract: A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger sampling of signals for generating signals of different timing/delay; then timing/delay of memory signals, such as clock, command, data and data strobe, can be adjusted and calibrated. In this way, the invention can avoid the use of delay lines while adjusting/calibrating memory signals, so as to reduce the negative effects of characteristics shift and variation of delay lines.Type: GrantFiled: January 26, 2005Date of Patent: October 28, 2008Assignee: VIA Technologies Inc.Inventors: Bowei Hsieh, Ming-Shi Liou
-
Patent number: 7418617Abstract: An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; and an adjusting unit connected to the multiplexing unit for receiving a signal and delaying to output the signal according to the first reference signal selected by the multiplexing unit.Type: GrantFiled: May 16, 2007Date of Patent: August 26, 2008Assignee: VIA Technologies Inc.Inventors: Bowei Hsieh, Ming-Shi Liou
-
Patent number: 7382665Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.Type: GrantFiled: September 28, 2006Date of Patent: June 3, 2008Assignee: Via Technologies, Inc.Inventors: Bo-Wei Hsieh, Ming-Shi Liou, Weber Chuang, Chi Chang
-
Publication number: 20070214378Abstract: An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; and an adjusting unit connected to the multiplexing unit for receiving a signal and delaying to output the signal according to the first reference signal selected by the multiplexing unit.Type: ApplicationFiled: May 16, 2007Publication date: September 13, 2007Inventors: Bowei Hsieh, Ming-Shi Liou
-
Patent number: 7257035Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.Type: GrantFiled: March 9, 2005Date of Patent: August 14, 2007Assignee: Via Technologies, Inc.Inventors: Bo-Wei Hsieh, Ming-Shi Liou, Weber Chuang, Chi Chang
-
Publication number: 20070130412Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.Type: ApplicationFiled: February 2, 2007Publication date: June 7, 2007Inventor: Ming-Shi Liou