Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units arid each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making die corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: A method is disclosed for utilizing at least one bit within the logical address code of a memory unit formed by Dynamic Random Access Memory (DRAM) to be the control code for interleaving the memory space to different memory ranks. First, the distributive rule of the data is defined. Next, the data is distributed to the memory ranks that the data belongs to according to the rule. Then, the data is physically accessed in one of the memory ranks.

Abstract: A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger sampling of signals for generating signals of different timing/delay; then timing/delay of memory signals, such as clock, command, data and data strobe, can be adjusted and calibrated. In this way, the invention can avoid the use of delay lines while adjusting/calibrating memory signals, so as to reduce the negative effects of characteristics shift and variation of delay lines.

Abstract: A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

Abstract: A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, bbuilding asingle bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: A method and device for controlling the data latch time. The method dynamically adjusts the latch time of the data strobe signal, so that the offset generated in the memory data signal or the data strobe signal due to the interference that results from the factors of the temperature variance or the voltage variance that impacts to the control chip and thus causes the inaccurate reading of the memory data can be avoided.

Abstract: The present invention relates to a method and system of calibrating the control delay time, providing effective calibration for the control delay time provided by a control chip to reach the optimal effect for effective reading. The control chip uses the connected buffer chip to produce a training sequence when the buffer chip enters a training mode. After the control chip receives the training sequence, the control chip will produce the training data to compare with the predefined pattern inside it and adjust the control delay time. Finally, the control chip will produce an optimal adjusting control delay time to allow the data strobe signal to control the effective retrieved range of the data.

Abstract: A method and device for controlling the data latch time. The method dynamically adjusts the latch time of the data strobe signal, so that the offset generated in the memory data signal or the data strobe signal due to the interference that results from the factors of the temperature variance or the voltage variance that impacts to the control chip and thus causes the inaccurate reading of the memory data can be avoided.