Abstract: The invention is directed to a method for testing a chip, wherein the chip comprises a plurality of devices. The method comprises steps of screening out at least one questionable device within the chip by applying a testing model on each of the devices with a normal operating factor set and then applying the testing model on each questionable device with a plurality of operating testing factor sets so as to verify a failure cause of the chip on each questionable device.

Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.

Abstract: A failure test method of word line-bit line short circuit in a split gate flash memory is provided. A well leakage-current test is performed to identify a sector with a failed memory cell. After being programmed, memory cells in the sector undergo a first read operation to generate a first bit map of the sector. After being erased, these memory cells in the sector undergo a second read operation to generate a second bit map of the sector. The first bit map and the second bit map are overlaid to identify the actual address of the failed memory cell.

Abstract: Method and device for providing double cell density in synchronous dynamic random access memory (SDRAM) and in double data rate synchronous dynamic random access memory (DDR SDRAM) are disclosed. In specific embodiments, a conventional photolithography technology is used to define a cell area on a semiconductor substrate and then a trench capacitor is formed in the cell area. After that, an array device active area is defined on the cell area and STIs are formed beside the array device active area in the semiconductor substrate. Next, a polysilicon layer is subsequently deposited, photolithographed and anisotropically etched to form an array device polysilicon layer. A gate oxide layer, a gate conductive layer and a gate cap are subsequently formed on the semiconductor substrate and cell area according to the following steps in specific embodiments.

Abstract: A novel SBTN (SraBibTacNbdOx) thin film which exhibits satisfactory ferroelectric properties is disclosed, wherein a lies between 0.5 and 1, b lies between 2 and 2.7, c lies between 1 and 1.4, d lies between 0.6 and 1.1, and x lies between 8 and 10. The composition of Sr0.8Bi2.5Ta1.2Nb0.9Ox wherein x lies between 9 and 10 is preferred. The Sr0.8Bi2.5Ta1.2Nb0.9Ox thin film is formed by two-target off-axis RF magnetron sputtering at a temperature down to about 600° C. One target is formed of Sr0.8Bi2.2Ta1.2Nb0.8O9, and the other target is formed of Bi2O3.