Patents by Inventor Ming-Shiang LIN
Ming-Shiang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10818562Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.Type: GrantFiled: June 27, 2018Date of Patent: October 27, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
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Patent number: 10797174Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.Type: GrantFiled: August 17, 2018Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
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Publication number: 20200273997Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
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Publication number: 20200273996Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Jin Cai, Tzu-Chung Wang, Tung Ying Lee
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Patent number: 10732209Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.Type: GrantFiled: September 30, 2019Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Ming-Shiang Lin, Chih-Sheng Chang, Carlos H. Diaz
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Patent number: 10707347Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: GrantFiled: January 23, 2019Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
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Patent number: 10670641Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.Type: GrantFiled: August 22, 2017Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chia-Cheng Ho, Ming-Shiang Lin, Chih-Sheng Chang, Carlos H. Diaz
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Publication number: 20200127138Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.Type: ApplicationFiled: January 23, 2019Publication date: April 23, 2020Inventors: Feng Yuan, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee, Jin Cai, Ming-Shiang Lin
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Publication number: 20200058784Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
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Publication number: 20200058763Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.Type: ApplicationFiled: September 5, 2019Publication date: February 20, 2020Inventors: Kai-Tai CHANG, Tung Ying LEE, Wei-Sheng YUN, Tzu-Chung WANG, Chia-Cheng HO, Ming-Shiang LIN, Tzu-Chiang CHEN
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Publication number: 20200033388Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.Type: ApplicationFiled: September 30, 2019Publication date: January 30, 2020Inventors: Cheng-Yi PENG, Chia-Cheng HO, Ming-Shiang LIN, Chih-Sheng CHANG, Carlos H. DIAZ
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Patent number: 10505040Abstract: A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.Type: GrantFiled: January 3, 2018Date of Patent: December 10, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Cheng Ho, Ming-Shiang Lin, Cheng-Yi Peng, Chun-Chieh Lu, Chih-Sheng Chang, Carlos H. Diaz
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Patent number: 10395937Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.Type: GrantFiled: August 29, 2017Date of Patent: August 27, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Tzung-Yi Tsai, Yen-Ming Chen, Dian-Hau Chen, Han-Ting Tsai, Tsung-Lin Lee, Chia-Cheng Ho, Ming-Shiang Lin
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Publication number: 20190164850Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.Type: ApplicationFiled: June 27, 2018Publication date: May 30, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
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Publication number: 20190097061Abstract: A method for manufacturing a semiconductor device comprises forming a first fin and a second fin on a first active region and a second active region of a semiconductor substrate, respectively. A first dummy gate is formed over the first fin and a second dummy gate is formed over the second fin, wherein the first dummy gate has a first gate width along a lengthwise direction of the first fin, the second dummy gate has a second gate width along the lengthwise direction of the second fin, the first gate width is different from the second gate width. At least one of the first dummy gate and the second dummy gate is removed. A ferroelectric layer is then formed over the semiconductor substrate, in which the first dummy gate and/or the second dummy gate is removed. At least one metal gate electrode is formed on the ferroelectric layer.Type: ApplicationFiled: January 3, 2018Publication date: March 28, 2019Inventors: Chia-Cheng HO, Ming-Shiang LIN, Cheng-Yi PENG, Chun-Chieh LU, Chih-Sheng CHANG, Carlos H. DIAZ
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Publication number: 20190067020Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Dian-Hau Chen, Han-Ting Tsai, Tsung-Lin Lee, Chia-Cheng Ho, Ming-Shiang Lin
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Publication number: 20190064238Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Inventors: Cheng-Yi PENG, Chia-Cheng HO, Ming-Shiang LIN, Chih-Sheng CHANG, Carlos H. DIAZ